Implementation of HighPerformance 32-bit

High-Valency Ling Adder

Under the guidance of

Mrs. E. Chitra, Asst. Prof. (Sr.G)
11-06-2013

By
K. V. Suresh Kumar
M.Tech VLSI Design

1581110060

Outline
Previous Work
Kogge stone Adder
Ladner fischer Adder
Ling adder with valency

Simulation Results
References
11-06-2013

Previous Work
A 32-bit Ling Adder is implemented by replacing H.Ling
proposed equations in CLA as follows.

pi = ai b i
gi = ai . bi

si = pi ci-1
ci= gi + pi . ci-1

ti = ai + bi
where ti = pi + gi

ci = gi + ti . ci-1
= ti . h i

si = pi c i-1
= pi (ti-1 . hi-1)
11-06-2013

The delay is compared with Carry Look Ahead

Adder and Ripple Carry Adder.
Adder(32-bit)

Delay(ns)

Power(W)

Ripple carry Adder

44.27 ns

0.168

Carry Look Ahead Adder

42.42 ns

0.215

Ling Adder(with H.Ling

6.096 ns

0.130

Equations)

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4-bit Kogge Stone Adder

A3=1 B3=1

A=1011
B=1100
S=0111

A2=0 B2=1

A1=1 B1=0

g3=1 p3=0

g2=0 p2=1

g1=0 p1=1

G3:2=1
P3:2=0

G2:1=0
P2:1=1

G1:0=0
P1:0=1

G3:0=1
P3:0=0

G2=C2=0

G1=C1=0

Cout=1
Black Cell
Gi= Gi+Pi.Gi-1
Pi=Pi . Pi-1

A0=1 B0=0
g0=0 p0=1

g = ai and bi
p = ai xor bi

G0=C0=0

Carry

ci= gi

G3=C3=1
p3
Cout=1

S3=0

Cin=0
p2
S2=1

p0

p1
S1=1

Sum
Si= pi xor ci-1

S0=1

a(7)
b(7)

gp7
g0(7)
p0(7)
bc10

g1(7)
p1(7)
bc11

g2(7)
p2(7)

g3(7)

P0(7)

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a(5)
b(5)

a(4)
b(4)

a(3)
b(3)

a(2)
b(2)

gp6

gp5

gp4

gp3

gp2

S7

g0(5)
p0(5)

g0(6)
p0(6)
bc8

bc6

bc9

bc7

g2(6)
p2(6)

gc5

g1(4)
p1(4)

gc4

g3(4)

g0(2)
p0(2)
bc1

g1(3)
p1(3)
bc3

g2(4)
p2(4)

g3(5)

g0(3)
p0(3)
bc2

bc5

g2(5)
p2(5)

g3(6)

g0(4)
p0(4)
bc4

g1(5)
p1(5)

g1(6)
p1(6)

gc6

gc7

Cout

a(6)
b(6)

g1(2)
p1(2)
gc2

g2(3)
p2(3)

a(1)
b(1)

a(0)
b(0)

gp1

gp0
g0(0)
p0(0)

g0(1)
p0(1)
bc0

gc0

g1(1)
p1(1)

g1(0)

gc1

g2(2)

g2(1)

g3(2)

g3(1)

g2(0)

gc3

g3(3)

P0(6)

P0(5)

P0(4)

P0(3)

P0(2)

P0(1)

S6

S5

S4

S3

S2

S1

P0(0)
S0

Cin

a(15) a(14)
b(15) b(14)

a(13)
b(13)

a(12)
b(12)

a(11)
b(11)

gp15 gp14 gp13

gp12

gp11

g0(15)
p0(15)
bc34

g0(14)
p0(14)

bc31

g1(15)
p1(15)
bc35

g0(13)
p0(13)
bc28

g1(14)
p1(14)
bc32

bc36

bc29

bc33

g3(15)
p3(15)
gc15

g4(15)

bc25

g1(13)
p1(13)

g2(14)
p2(14)

g2(15)
p2(15)

g0(12)
p0(12)

bc30

g3(14)
p3(14)
gc14

bc22

g1(12)
p1(12)

g2(12)
p2(12)
bc27

g3(13) g3(12)
p3(13) p3(12)
gc13

g4(14) g4(13)

gc12

g4(12)

P0(15) P0(14) P0(13) P0(12)

S15

Cout

S14

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S13

S12

gp10

g0(11)
p0(11)

bc26

g2(13)
p2(13)

a(10)
b(10)

a(9)
b(9)

a(8)
b(8)

a(7)
b(7)

gp9

gp8

gp7

g0(10)
p0(10)
bc19

g0(9)
p0(9)
bc16

bc13

g1(11) g1(10)
p1(11) p1(10)
bc23

bc20

g2(11)
p2(11)
bc24

gc11

g4(11)

g1(9)
p1(9)
bc17

g3(10)
p3(10)

gc10

g4(10)

P0(11) P0(10)
S11

S10

bc10

bc14

bc18

bc11

bc15

gc9

bc12

gc8

g4(9)

g0(6)
p0(6)
bc6

g1(6)
p1(6)

a(3)
b(3)

a(2) a(1) a(0)

b(2) b(1) b(0)

gp4

gp3

gp2

g0(4)
p0(4)
bc4

g1(5)
p1(5)
bc7

g2(6)
p2(6)
gc6

g3(7)
p3(7)

a(4)
b(4)

g0(5)
p0(5)

bc9

g2(7)
p2(7)

g3(8)
p3(8)

gp5

bc8

g1(7)
p1(7)

g2(8)
p2(8)

g3(9)
p3(9)

gp6

g0(7)
p0(7)

g1(8)
p1(8)

g2(9)
p2(9)

g2(10)
p2(10)
bc21

g3(11)
p3(11)

g0(8)
p0(8)

a(6) a(5)
b(6) b(5)

bc2

g1(4)
p1(4)

bc1

bc3

g2(3)
p2(3)

g2(4)
p2(4)

gc5

gc4

g3(5)

bc0

g1(2)
p1(2)
gc2

Cin

g0(1) g0(0)
p0(1) p0(0)

g0(2)
p0(2)

g1(3)
p1(3)

bc5

g2(5)
p2(5)

g3(6)

g0(3)
p0(3)

gp1 gp0

gc0

g1(1)
p1(1)

g1(0)

gc1

g2(2) g2(1) g2(0)

gc3

g3(4)

g3(3)

g3(2)

g3(1)

gc7

g4(8)

P0(9)

P0(8)

S9

S8

g4(7)

g4(6)

g4(5)

g4(4)

g4(3)

P0(7) P0(6) P0(5) P0(4) P0(3) P0(2) P0(1)

S7

S6

S5

S4

S3

S2

S1

P0(0)
S0

32 bit Kogge Stone Adder

11-06-2013

Ling Adder with valency

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R(2)31:30

R(5)31:22

R(2)31:12

R(5)21:12

R(3)11:6

R(3)5:0

R(2)11:0

R(2)31:0

11-06-2013

32-bit Adder carry tree with valency 2x3x2(12 bit) and 2x5x2(20 bit)

Ling Adder with Valency 2x3x2 and 2x5x2

11-06-2013

Steps to reduce delay

If the load of any gate is larger than required the reduction in load is obtained
either by reducing the wire load or by fan-out load.
Wire load reduction is possible by placing the driving gate and driven gates
close to each other.
Fan-out reduction can be obtained by inserting the inverter after that gate and
driving the gates on non-critical path through that inverter and gate on critical
path directly.
Techniques like shielding reduce the wire capacitance of long wires by placing
the power and ground rails parallel to that wire.
By connecting input which is available late to the faster input of the gate can
also reduce the total delay.
Some of the gates have very high input capacitance so the delay through that
gate is longer compared to others, avoiding such gates and reformulation of
equations to use better gates reduces the overall delay.
11-06-2013

Delay comparison
Adder(32-bit)

Delay(ns)

Power(W)

Ripple carry Adder

44.27 ns

0.168

Carry Look Ahead

42.42 ns

0.215

Kogge stone Adder

13.897 ns

0.167

Ling Adder(with H.Ling

6.096 ns

0.130

6.026 ns

0.349

Adder

Equations)
Ling Adder with

Valency
11-06-2013

Advantages

Compared with normal CLA adder:

ci = gi + ci-1 ti
= gi + gi-1 . ti + gi-2 . ti-1. ti + + ti . ti-1 . . t0 . C-1
hi = gi + gi-1 +

gi-2 . ti-1 + + ti-1 . ti-2 . . t0 . h-1

Each product term in hi has one less AND gate

correspondingly
11-06-2013

References
[1] Taskin Kocak, Preeti Patil, Design and Implementation of High-Performance
High-Valency Ling Adders. 978-1-4673-1188-5/12/ 2012 IEEE
[2] Dayu Wang, Xiaoping Cui, Xiaojing Wang, Optimized design of Parallel Prefix Ling
Adder, International Conference on Electronics, Communications and Control
(ICECC) 2011.
[3] Dimitrakopoulos. G, Nikolos. D, High-speed
adders, IEEE Transactions on Computers, Feb. 2005.

parallel-prefix

VLSI

Ling

[4] Matthew Keeter, David Money Harris, Andrew Macrae, Rebecca Glick, Madeleine
Ongand Justin Schauer, Implementation of 32-bit Ling and Jackson Adders,
Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and
Computers (ASILOMAR), 2011
[5] Adder Designs, http://www.acsellab.com/Projects/fast_adder/adder_designs.htm
11-06-2013

Thank you
11-06-2013