Intel Hub Architecture Overview

Chapter 1

Copyright 1996-2003 Intel Corp.

PC Chipset: Bus Architecture

Intel Hub Architecture

OBJECTIVES: At the end of this section, the student will be able to do the following:
Explain Identify

Intel Hub Architecture block diagram Intel Hub Link Bus attributes

Explain
Explain

the MCH, GMCH and ICH block diagrams

the FWH block diagram the CNR interface

Describe

IATT Web Site:http://iatt.intel.com

PC Chipset: Bus Architecture CH-1 Slide-2

M-1

Host Bus (PSB) 100/133/200MHz 64-bit AGP Bus

Processor

System Memory

North Bridge (MCH)

Clock Gen

Host Clock PCI Clock USB Clock Hublink Clock

HubLink Bus
CNR

SM Bus
South Bridge (ICH)

The Chipset consists of the North Bridge, South Bridge and Firmware Hub

PCI Bus 33 MHz 32-bit

LAN Audio USB IDE Parallel

PC Chipset: Bus Architecture

LPC Bus
Mouse

FWH

SIO

Keybrd Floppy Serial

CH-1 Slide-3

Intel PC Chipsets
Include Various

North Bridge, South Bridge and Firmware Hub

chipsets available from Intel to meet specific performance requirements

Value PC (810, 815)

Pentium SDRAM Integrated

III or Celeron Processor

Graphics controller (Direct AGP)

Mainstream & Performance PCs (845, 850)

Pentium SDRAM, Support

4 Processor DDR or RAMbus for AGP, DVO or Direct AGP

Support

for Hyper-Threading Technology (later 845s)

CH-1 Slide-4

PC Chipset: Bus Architecture

Chipset Components
The

Northbridge may be either:

between the CPU and the rest of the system

Memory Controller Hub (MCH)

Interfaces

Memory AGP Bus Hublink Bus

Graphics and Memory Controller Hub (GMCH)

Includes

integrated graphics accelerator

Supports either: (depends on version) Direct AGP - fully integrated graphics engine - no external AGP slot - used for Value PC or AGP 2.0 (with AGP slot) Support for analog video, Digital Video Out (DVO) and Display Data Channel (DDC)
PC Chipset: Bus Architecture CH-1 Slide-5

M-1

Which device supports "Direct AGP"? 1: MCH 2: ICH 3: GMCH

4: FWH

PC Chipset: Bus Architecture

CH-1 Slide-6

Chipset Components
The

South Bridge or I/O Controller Hub (ICH)

Bus

Interfaces to I/O devices

PCI IDE USB LPC

bus to Firmware Hub and Super I/O (Legacy I/O)

The

Firmware Hub (FWH)

Stores BIOS code/data in 512KB or 1MB flash memory Random number generator Can be reprogrammed in place

PC Chipset: Bus Architecture

CH-1 Slide-7

 Proprietary

point-to-point interface between MCH and

ICH

Expandable to multiple Hublink bus structure in some chipsets

Eight

bit data bus, two strobe signals, 3 special signals

66.6MHz clock signal derived from AGP clock May also be 16 bit data and/or 100MHz clock

Data

can be transferred at 4 bytes per clock cycle design and operation is Intel proprietary

4 bytes x 66.6MHz clock = 266MB/sec

Hublink

PC Chipset: Bus Architecture

CH-1 Slide-8

 Each

contain PCI devices which are designated with a one byte ID--the MCH contains 2 devices; GMCH has 3.

Device 0: Host to Hub Bridge- Resides on PCI bus 0

Connects

Host bus to PCI bus 0 interfaces with system memory controller to AGP bus to extend outside the MCH

Device 1: PCI to AGP Bridge- Resides on PCI bus 0

Connects AGP

bus may be designated as BUS 2

When

card is plugged into AGP slot it will be Bus 2:Device 0

video out (VGA) Data Channel (DDC for plug and play monitor)
CH-1 Slide-9

Device 2: Graphics Accelerator (GMCH only) on PCI Bus 0

Analog Digital

video out

Display
PC Chipset: Bus Architecture

MCH PCI Devices

ADDR DATA CTRL

Host Bus

BUS 0 DEVICE 0
Host-Hub Bridge B0:D0:F0

System Memory Interface

AGP Bus (PCI Bus 2)

BUS 2 DEVICE 0
AGP Slot B2:D0:F0

BUS 0 DEVICE 1
PCI-AGP Bridge B0:D1:F0

SCS[11:1]# SMA[12:1] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] RDCLK0 RDCLKIN

Logical PCI Bus 0

Hub Interface

PC Chipset: Bus Architecture

HL [11:0]

HL_STB

CH-1 Slide-10

82815 GMCH PCI Devices

ADDR DATA CTRL

Host Bus

BUS 0 DEVICE 0
Host-Hub Bridge B0:D0:F0

System Memory Interface

AGP Bus (PCI Bus 2)

BUS 2 DEVICE 0
AGP Slot B2:D0:F0

BUS 0 DEVICE 1
PCI-AGP Bridge B0:D1:F0

SCS[11:1]# SMA[12:1] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] RDCLK0 RDCLKIN

Analog Display Out Digital Video Out Display Data Channel

BUS 0 DEVICE 2
Graphics Accelerator B0:D2:F0

Logical PCI Bus 0

Hub Interface

PC Chipset: Bus Architecture

HL [11:0]

HL_STB

CH-1 Slide-11

 The

ICH and MCH each contain PCI devices which are designated with a 1 byte hex number--the ICH has three:

Device 1E: Hub to PCI Bridge- Resides on PCI bus 0

Connects

PCI bus 0 to PCI bus1 to extend outside the ICH

Device 1F: Multi-function- resides on PCI bus 0

PCI IDE

to LPC Bridge for interface to firmware hub and Super I/O controller controller

SMB

Two

USB controllers
Audio Controller Modem Controller 10/100 Mbit/sec Ethernet and 1Mbit/sec Home PNA
CH-1 Slide-12

AC97 AC97

Device 08: LAN controller- Resides on PCI bus 1

Supports

PC Chipset: Bus Architecture

ICH PCI Devices

HL [11:0] HL_STB

PCI Bus 1

Logical PCI Bus 0

LAD [3:0] LFRAME# LDRQ[0:1]# PDCS1# PDA[2:1]

Hub Interface

BUS 0 DEVICE 1E
HUB-PCI Bridge B0:D1E:F0

PCI-LPC Bridge B0:D1F:F0 USB Ctr. 1 B0:D1F:F2 IDE Controller B0:D1F:F1 USB Ctr. 2 B0:D1F:F4 SMB Controller B0:D1F:F3

BUS 1 DEVICE 8
LAN Cntr. B1:D8:F0

LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] USBP0[P:N] USBP1[P:N] OC[1:0]# USBP2[P:N] USBP3[P:N] OC[3:2]# SMBDATA SMBCLK AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN0 AC_SDIN1
CH-1 Slide-13

PDD[15:0] PDDREQ PDDACK# PDIOR# PDIOW# PIORDY

DEVICE 1F

Audio Ctr. B0:D1F:F5

Modem Ctr B0:D1F:F6 AC97 Controller

PC Chipset: Bus Architecture

ICH PCI Devices

Chipset

data books use DECIMAL numbers to identify devices: e.g., Device 1Eh = 30(10) ; Device 1Fh = 31(10)
PCI Bus 1
Hub Interface

BUS 0 DEVICE 1E
HUB-PCI Bridge B0:D1E:F0

Chipset Data Book Description

Functional Description Hub-PCI Bridge PCI-LPC Bridge IDE Ctlr USB Ctlr 1 SMBus Ctlr

Logical PCI Bus 0

PCI-LPC Bridge B0:D1F:F0

BUS 1 DEVICE 8
LAN Cntr.
B1:D8:F0

Bus:Dev:FN (in decimal)

0 : 30 : 0 0 : 31 : 0 0 : 31 : 1 0 : 31 : 2 0 : 31 : 3

USB Ctr. 1 B0:D1F:F2 IDE Controller B0:D1F:F1

USB Ctr. 2 B0:D1F:F4 SMB Controller B0:D1F:F3

0 : 31 : 4
Audio Ctr. B0:D1F:F5

USB Ctlr 2
Audio Ctlr Modem Ctlr LAN Ctlr
CH-1 Slide-14

0 : 31 : 5
AC97 Controller

DEVICE 1F
Modem Ctr B0:D1F:F6

0 : 31 : 6 1: 8: 0

PC Chipset: Bus Architecture

M-1

The MCH and ICH are connected together by:

1: the PCI Bus 2: the LPC Bus 3: the Hublink Bus

4: the ISA Bus

PC Chipset: Bus Architecture

CH-1 Slide-15

 The

FWH contains
into 64KB lockable blocks

512KB or 1MB of Flash ROM for storing BIOS code/data

Arranged

Block Lock Registers

One

for each 64KB block to lock read or write ability

status of FGPI pins

General Purpose Register

Reflects

Typical use of FGPI pins are to gather misc. data such as jumper settings (BIOS recovery jumper)

Random Number Generator

Can

produce Random Numbers used for data encryption

RNG

may or may not be present (depends of version of FWH)

CH-1 Slide-16

PC Chipset: Bus Architecture

Firmware Hub (FWH)

Block Lock Regs
LPC Bus

LFRAME / FWH4 LAD[3:0] / FWH[3:0] ID[3:0] FGPI[4:0]

General Purpose Inputs

FWH Interface

Flash ROM 512KB (1MB)

Random Number Generator

Device shown as used in FWH Mode See chapter 3 for details on AAMux Mode
PC Chipset: Bus Architecture CH-1 Slide-17

The CNR provides the PC Industry the opportunity to deliver a flexible and cost reduced method to implement subsystems widely used in "connected PCs".

LAN Home networking MODEM & DSL

Wireless Audio USB

The CNR Specification is an open industry specification and is supported by OEMs, IHV card manufacturers, silicon suppliers and Microsoft. CNR Spec. calls for cards to be PnP: an EEPROM on the CNR card contains configuration information.

PC Chipset: Bus Architecture

Upper three SMB Address bits of CNR card determined by pull up resistors on the system board.

CH-1 Slide-18

CNR Interface to ICH

EE_SHCLK

+5v

M-3

ICH
BUS 0 DEVICE 1F
USB Ctr. 2 B0:D1F:F4
OC

CNR EEPROM Interface

EE_DIN EE_DOUT EE_CS LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] * USB1[P:N] * OC# SMBDATA SMBCLK

SMB_A2 SMB_A1 SMB_A0

BUS 1 DEVICE 8
LAN Cntr. B1:D8:F0

Used to strap lower three bits of CNR SMB Address

(in this case: 110)

SMB Controller B0:D1F:F3

AC_RST#

Audio Ctr. B0:D1F:F5 AC97 Controller

AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN0 AC_SDIN1

Modem Ctr B0:D1F:F6

CNR Connector

Used to communicate with EEPROM on CNR card (see appendix)

+12v -12v +3.3v +5v
CH-1 Slide-19

PC Chipset: Bus Architecture

* USB lines may alternatively be routed from USB Host Controller ASIC

CNR Connector Pinout

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 RESERVED RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD1 LAN_RSTSNC GND LAN_RXD2 LAN_RXD0 GND RESERVED +5Vdual USB_OC# GND -12V +3.3VD KEY GND EE_DOUT EE_SHCLK GND SMB_A0 SMB_SCL CDC_DN_ENAB# GND AC97_SYNC AC97_SDATA_OUT AC97_BITCLK RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD2 LAN_TXD0 GND LAN_CLK LAN_RXD1 RESERVED USB+ GND USB +12V GND +3.3Vdual +5VD KEY GND EE_DIN EE_CS SMB_A1 SMB_A2 SMB_SDA AC97_RESET# AC97_SDATA_IN2 AC97_SDATA_IN1 AC97_SDATA_IN0 GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30

A1

PC Chipset: Bus Architecture

CH-1 Slide-20

Chapter 1 Quiz
1) The FWH is accessed via the:
A) LPC Bus B) PCI Bus Highway Bus C) Hublink Bus D) Beaverton-Hillsdale

M-4

2) Which chip controls PCI Bus 1?

A) ICH B) MCH C) FWH
D) SIO

3) The Intel Hublink Bus can transfer data at 3.2GB/s (True / False) 4) Which of the following devices is routed to the CNR connector?
A) IDE controllerC) AGP controller B) Floppy controller D) Audio Controller
PC Chipset: Bus Architecture CH-1 Slide-21

REVIEW & SUMMARY

Intel

Hub Architecture
(GMCH in value PC applications)

Contains:
MCH ICH FWH

Intel

Hub Link Bus attributes

Can transfer data between the MCH and ICH at 266MB/s Intel Proprietary

PC Chipset: Bus Architecture

CH-1 Slide-22

REVIEW & SUMMARY

MCH

and GMCH Control Memory and Graphics

MCH: AGP controller GMCH: Integrated Graphics Accelerator (Direct AGP)

ICH

contains:
PCI bus 0 to PCI bus1 to extend outside the ICH

Hub to PCI Bridge

Connects

PCI to LPC Bridge for interface to firmware hub and Super I/O IDE controller SMB controller Two USB controllers AC97 Audio Controller AC97 Modem Controller

PC Chipset: Bus Architecture CH-1 Slide-23

REVIEW & SUMMARY

Firmware

Hub

Contains BIOS
Utilizes Flash ROM technology
Can

be reprogrammed in place on the motherboard

Communications

and Networking Riser

Interface to devices in ICH:

MODEM Audio USB SMB

controller

controller

controller Controller

PC Chipset: Bus Architecture

End of Chapter 1

CH-1 Slide-24