Enhanced Scan Based Flip-Flop for Delay Testing

By Sudheer Vemula

4/28/05

Vemula: ELEC7250

Problem to be solved:

To perform delay test, two vectors, V1 and V2, have to be applied in sequence

V1 For initializing the output of a particular path under test V2 To observe the transition at the output

The problem is, if we want to apply two independent vectors to the scan chain of flip-flops, we will loose the initialization of the circuit. This problem can be solved by inserting hold latches, with an additional HOLD signal, to each scan flip-flop.

Area over head and delay in the signal path are increased.

Problem to be solved:- We need hold latches which have less area overhead and time delay.
Vemula: ELEC7250 2

4/28/05

Background

Two widely used delay test techniques are Launch from Capture

Operation of Enhanced Scan Hold Flip-Flop:

V2 is obtained from the response of V1 V2 is one bit shift of V1

PI Combinational Circuit

PO

Launch from Shift

The vector V2 cant be arbitrary in both the techniques.

Scan Out HL

CLK TC

SFF SFF Scan In

CLK TC

HL Hold

4/28/05

Vemula: ELEC7250

Hold Latches
HOLD/TC

HOLD
HL

HOLD D Q Q

D CLK

Q Q

CLK

M U X

CLK

MUX based Latch

Enhanced Scan Flip-Flop

4/28/05

Both designs of hold latches add delay, which will affect the performance. The area overhead is also present.
Vemula: ELEC7250 4

Supply Gating Scheme

This scheme is applied to the combinational logic present after the flip-flop (First Level Hold). The state of the combinational logic is held in response to the first pattern by gating the VDD and GND of the first level logic gates. Disadvantage:

VDD
TC

PMOS Network IN NMOS Network OUT

There might be leakage of charge due to the next level of logic gates
Vemula: ELEC7250

TC

GND
4/28/05 5

Solution

The output should be pulled to either VDD or GND. Add a latch. Another Disadvantage:Power dissipation during the normal operation. Solution Block the operation of the latch during the normal operation of the circuit.

V VDD DD
TC

PMOS PMOS Network Network IN NMOS NMOS Network Network

TC

TC

OUT OUT

TC TC

GND GND

For Normal Operation TC = 1

For Hold Mode TC = 0

4/28/05 Vemula: ELEC7250 6

Results
ISCAS 89 CKTs Decrease in Power Dissipation Percentage Percentage Percentage Percentage Percentage Percentage improvement improvement improvement improvement improvement improvement over mux (flip- over over mux over over mux over flops/fanout enhanced enhanced enhanced ratio) scan scan scan S298 -1.93(14/2.5) 7.28 77.01 66.54 68.69 76.92 S344 13.02(15/2.1) 20.88 65.15 52.67 79.90 86.05 S641 59.23(19/1.0) 62.91 68.54 50.92 86.94 90.34 S838 -22.31(32/3.0) -11.27 71.25 63.52 60.06 70.80 S1196 47.90(18/1.3) 52.61 81.75 71.26 94.78 95.96 S1423 11.85(74/2.2) 19.81 72.74 55.83 95.83 96.68 S5378 36.22(179/1.6) 41.98 73.65 65.21 90.83 93.45 S9234 14.01(211/2.1) 21.78 82.70 68.39 83.56 88.87 S13207 53.41(638/1.14) 57.62 86.27 78.18 106.05 104.35 S15850 36.09(534/1.57) 41.87 80.64 76.47 86.06 89.73 S35932 36.48(1728/1.6) 42.22 81.19 71.49 91.75 94.44
4/28/05 Vemula: ELEC7250 7

Area Overhead

Delay Overhead

Conclusions

The additional transistors in both PMOS and NMOS networks will increase the load at the output of the flip-flop, which will cause some additional delay compared to normal operation of the circuit without hold latch. If fan outs are present at the output of the flip-flops, this will cause an increase the area and delay overhead.

For smaller circuits with more fan outs, MUX based latch may give better results for some cases.

There is an average reduction of 33% in area overhead with an average improvement of 71% in delay overhead and 90% in power overhead during normal mode of operation compared to enhanced scan implementation.
Vemula: ELEC7250 8

4/28/05

Reference
[1] S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application, Proc. Design, Automation and Test in Europe, pp. 1136-1141, 2005

4/28/05

Vemula: ELEC7250