Jaeger/Blalock

10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 1
Chapter 9
Bipolar Logic Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 2
Chapter Goals
Bipolar switch circuits
Emitter-coupled logic (ECL)
Behavior of the bipolar transistor as a saturated switch
Transistor-transistor logic (TTL)
Schottky clamping techniques for preventing saturation
Operation of the transistor in the inverse-active region
Voltage reference design
BiCMOS logic circuits

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 3
The Current Switch
(Emitter-Coupled Pair)
The building block of
emitter-coupled logic
(ECL) is the current
switch circuit which
consists of matched
components
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 4
The Current Switch
Depending on how much higher or lower the input
voltage v
I
is compared to V
REF
, the reference
current will switch to one of the legs creating a
voltage v
C1
or v
C2

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 5
Mathematical Model for Static Behavior
of the Current Switch
The previous figure showed the ideal case for
switching the currents between the two legs, but in
real BJTs current will be present in both legs
depending upon v
BE
of each BJT in the pair

The collector current difference is given by:
|
|
.
|

\
|

=
T
BE BE
EE F C C
V
v v
I i i
2
tanh
2 1
2 1
o
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 6
Current Switch Analysis for v
I
> V
REF

Given the circuit shown under the given bias conditions (v
I

is 300mV larger than V
REF
), the majority of current will
flow in the left leg
0
0
2 2 2
1 1 1
2
1
~ ~ =
~ ~ =
~
~
C E F C C C
C EE F C E F C C C
E
EE E
R i R i v
R I R i R i v
i
I i
o
o o
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 7
Current Switch Analysis for v
I
< V
REF
Given the circuit shown under the given bias conditions (v
I

is 300mV less than V
REF
), the majority of current will flow
in the right leg

C EE F C E F C C C
C E F C C C
EE E
E
R I R i R i v
R i R i v
I i
i
o o
o
~ ~ =
~ ~ =
~
~
2 2 2
1 1 1
2
1
0
0
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 8
The Emitter-Coupled Logic (ECL) Gate
The outputs of the previous current switch have the value of
either 0V or 0.6V
The difference of the input and output of the current switch is
exactly one base-emitter voltage drop
For a complete ECL gate, the voltages are shifted by a base-
emitter drop as shown in the figure
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 9
ECL Gate Summary
v
I
v
O1
v
O2
I
IN

V
REF
+ 0.3V = -0.7V -1.3V -0.7V +14.3A
V
REF
- 0.3V = -1.3V

-0.7V -1.3V 0
2
0
1
1
L H
REF
IN
F
EE
B IN
V V
V
i
i
i i
+
=
=
+
= =
|
For v
I
= -0.7V
For v
I
= -1.3V
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 10
ECL Gate Benefits
ECL gates produce both true and complemented
outputs
ECL gates are fast since it the BJTs are always in
forward active mode, and it only takes a few
tenths of a volt to get the output to change states,
hence reducing the dynamic power
ECL gates provide near constant power supply
current for all states thereby generating less noise
from the other circuits connected to the supply
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 11
Noise Margins for the ECL Gate
C EE
T
T L H
T L C C L OL
T
T REF IH
T H C C H OH
T
T REF IL
R I V
V
V
V
V
NM NM
V V R i V V
V
V
V V V
V V R i V V
V
V
V V V
= A
(

|
|
.
|

\
|

A
+
A
= =
+ = + =
|
|
.
|

\
|

A
+ =
= =
|
|
.
|

\
|

A
=
1 ln 1
2
1 ln
1 ln
1
1
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 12
Current Source Implementation
Instead of using actual current sources for the current
biasing in an ECL gate, resistors can be used as shown
below
Note that the currents in
the emitter-follower legs
will not be equal since
the output voltages will
be different. This will
instead be looked at as
an average value
between the two legs.
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 13
ECL Gate Design Example
Design an ECL gate with the circuit configuration shown
on the previous slide to operate at a power supply of 3.3V
knowing the following information
mA I
V V
V V
V V
V V
E
REF
L
H
3 . 0
0 . 1
6 . 0
3 . 1
7 . 0
2
=
=
= A
=
=
And a mean emitter
follower current of 0.1mA
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 14
ECL Gate Design Example
For v
I
= 1.3V, Q
1
will be off causing the
common emitter voltage to be 1.7V. R
EE
can now
be calculated by the following:


And R
C2
is:
O =

= k
mA
V
R
EE
33 . 5
3 . 0
) 3 . 3 ( 7 . 1
( )
O = =
A
~
+ +
A
=
+
A
= k
mA
V
I
V
I I I I
V
I I
V
R
E B B B C B C
C
0 . 2
3 . 0
6 . 0
2 2 4 2 2 4 2
2
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 15
ECL Gate Design Example
For v
I
= 0.7V, Q
2
will be off causing the
common emitter voltage to be 1.4V. I
E1
can now
be calculated by the following:


Now R
C1
can be found as:

( )
A
k
V
I
E
357
2
3 . 3 4 . 1
1
=
O

=
O = =
A
~
+
A
= k
mA
V
I
V
I I
V
R
E B C
C
68 . 1
357 . 0
6 . 0
1 3 1
1
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 16
ECL Gate Design Example
Finally, R can be calculated by using the mean
output voltage and current levels
( )
O =
+
~

+
= k
mA
V
I
V
V V
R
E
EE
L H
23
1 . 0
3 . 3 1
2
3
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 17
The ECL OR-NOR Gate
Three variations of
a 3-input ECL OR-
NOR Gate
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 18
The Emitter Follower
The main purpose of the emitter follower in ECL gates is
to create a level shift in the output
The figure shows both the circuit and its transport model
for the forward- active region
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 19
The Emitter Follower
The emitter
follower is called
such since the
voltage at the
emitter follows the
votlage at the base,
but at an offset
which can be seen
in the ideal VTC
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 20
The Emitter Follower with a
Resistor Bias
As previously shown, the current source can be replaced
with a resistor bias scheme
This technique will cause a change in v
BE
due to the
variation of i
E
as v
O
changes, but this change is minimal
and v
O
= v
I
0.7

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 21
The Emitter Follower with a
Resistor Load
The addition of a resistive load will alter the
minimum voltage of an ECL gate (when i
E
=0)
( )
EE
E L
L
MIN
V
R R
R
V
+
=
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 22
Emitter Dotting or Wired-OR Logic
The circuit shown in
the figure exhibits two
emitter followers in
parallel with a common
output
The result for the
shown bias condition
implies that Q
2
is cutoff
and Q
1
has to handle
2I
EE

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 23
Wired-OR Logic Function
The parallel emitter on the
previous slide can be used
to implement an OR
function as shown in the
figure, also called the
Wired-OR
This is distinct to ECL
logic since in most logic
families, the outputs
cannot be tied together
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 24
Design of Reference Voltage Circuits
So far the implementation of the V
REF
signal has not been
discussed, but it can be created with a simple resistor voltage
divider as seen below
The Thveninequivalentcircuitisusedtoshowthatthe
voltageatthebaseofQ
2
willnotbeexactly1Vas
designedduetothefactthattherewillbearesistive
voltagedropacrosstheThveninresistanceinducedbyi
B2

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 25
Temperature Compensation
Since the v
BE
of the BJT changes by approximately 1.8mV/K,
it is obvious that when R
EE
is used to replace the current switch
current source, that i
E2
will vary with temperature
Two techniques are shown below that temperature compensate
(track) the variation
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 26
Diodes in Bipolar Integrated Circuits
In ICs it is desired to have a diode match the base-emitter
characteristics of a BJT (temperature compensation circuit)
Since a normal diode structure takes about the same
amount of Silicon area as a BJT, it is just as easy to tie
base to the collector (diode-connected) of a BJT to create a
diode
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 27
ECL Power Dissipation
The static average power of an ECL inverter can
be found by the following (referring to the shown
circuit):
( )
4 3
I I I V P
EE EE
+ + =
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 28
Power Reduction
Approximately 40% of the power is dissipated by the
emitter-follower stages
One technique to reduce this current is to make the bias the
emitter-follower resistors at a less negative value thereby
reducing the current, however this requires an additional
power supply
Another technique is to share the current in the manner
shown on the next slide (similar to the wired-OR),
however any output that is not driving another logic gate
needs to be terminated with a resistor to the negative
power rail
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 29
Power Reduction
Changing the power
supply
Repartitioned ECL gate
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 30
Gate Delay
ECL inverter with all
capacitors shown
Simplified ECL gate
model for dynamic
response
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 31
Gate Delay
The gate delays and voltages can be calculated
with following expressions:
( ) ( )
L C PHL PLH
C EE
PLH C PHL C
C R
R I
v v
69 . 0
2
2 2
= =
= =
t t
t t
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 32
Power-Delay Product
The below figures illustrate the tradeoff of power
and speed for ECL gates
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 33
The Saturating Bipolar Inverter
One of the most basic
circuits for BJT logic
gates is the saturating
bipolar inverter
The resistor pull the
output high when v
I
is
low, and the output goes
to v
CE
when v
I
is high
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 34
Saturating Bipolar Inverter Example
Design a saturating bipolar inverter such that the
collector saturation voltage is 0.1V with a
collector of 10A. Find the base current required to
achieve these specs given the following:
mV V
T
R
F
25
1 . 0
20
=
=
=
|
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 35
Saturating Bipolar Inverter Example
First find the minimum V
CE
:



Next find :


V V V V
R
R
T
R
T CEMIN
6 . 0
1
ln
1
ln =
|
|
.
|

\
|
+
=
|
|
.
|

\
|
=
|
|
o
6 . 54
025 . 0
1 . 0
exp exp =
|
.
|

\
|
=
|
|
.
|

\
|
= I
V
V
V
V
T
CESAT
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 36
Saturating Bipolar Inverter Example
Finally, solving for I
B
:
( )
A
A I
I
R
R
F
F
C
B
92 . 2
6 . 54
11
1
1
1
6 . 54 1 . 0
20
1
20
10
1
1
1
=
(
(
(
(
(
(
(

|
.
|

\
|
+
+
=
(
(
(
(

I
+
I
+
>
o
|
|
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 37
Load Line Visualization
The following is a
typical load line
characteristic for
a saturating
bipolar inverter
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
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Chap 9 - 38
Switching Characteristics of the
Saturated BJT
An important switching factor
is that when excess base
current required to drive the
BJT into saturation is stored
into the base region. This
charge needs to be removed
before the BJT can be turned
off.
This delay is called the
storage time (t
S
)
The figures show typical
switching characteristics
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 39
Switching Characteristics of the
Saturated BJT
The storage time delays can be calculated using the
following expressions:





Where
F
and
R
are the forward and reverse common-base
current gains, and
F
and
R
are the forward and reverse
transit times

( )
F R
R R F F
S
BR
F
CMAX
BR BF
S S
I
i
I I
t
o o
t o t o
t
|
t

+
=
|
|
|
|
.
|

\
|

=
1
ln
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 40
A Transistor-Transistor Logic (TTL)
Prototype
TTL has the workhorse for digital systems such as
microprocessors for years
The basic structure for the TTL inverter is shown
below
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 41
TTL Inverter Operation
The two figures show the bias points for the two standard
low and high inputs
The output ranges from V
OL
= 0.15V to V
OH
= 5V
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 42
Power in the Prototype TTL Gate
The power the TTL inverter dissipates for a low
output is:


The power the TTL inverter dissipates for a low
output is:

( )
IH I B C CC IH I CC CC L
i v i i V i v i V P + + = + =
1 2
IL I B CC IL I CC CC H
i v i V i v i V P + = + =
1
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 43
V
IH
, V
IL
, and Noise Margins for the
TTL Prototype
The figure shows where V
IL

and V
IH
occur, and they can
be approximated by the
following expressions using
standard TTL values:
V NM
V NM
V V V V
V V V
V V V V V
V V V
H
L
CESAT L OL
BESAT IH
H T H OH
CESAT IL
2 . 4 8 . 0 0 . 5
51 . 0 15 . 0 66 . 0
15 . 0
8 . 0
5
66 . 0 7 . 0
2
2
1
= ~
= ~
= = ~
= ~
= ~ ~
= ~
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 44
Fanout Limitations of the TTL Prototype
For NMOS, CMOS,
and ECL gates, fanout
was not investigated
in detail since the
input current to these
gates were considered
to be zero. However,
this is not the case for
TTL as seen in the
figure.
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 45
Fanout Limitations of the TTL
Prototype Example
For a TTL gate find:
a) the fanout limit (N) for a V
CESAT2
less that 0.1V
b) the input current i
IH
and fanout limit for v
I
= v
OH

assuming
R1
=2
Giventhefollowing:


V V
V V
V V
BE
BESAT
CESAT
R
F
7 . 0
8 . 0
04 . 0
25 . 0
40
1
=
=
=
=
=
|
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 46
Fanout Limitations of the TTL
Prototype Example
First find N for v
O
= V
L
:



Next find the max i
C
:

) 03 . 1 ( 45 . 2 ) ( ) (
03 . 1
4
1 . 0 8 . 0 5 5
mA N mA i N
R
v V
i N i i
mA
k
V
R
v V
i
IL
C
O CC
IL R C
B
I BESAT
IL
+ = +

= + =
=
O

=

=
( )
( )
7 . 17
6 . 54 333 . 0
20
1
6 . 54 25 . 0
1
1
40
6 . 54
025 . 0
1 . 0
exp
=
+

s
=
|
.
|

\
|
= I
FOR
V
V
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 47
Fanout Limitations of the TTL
Prototype Example
Continuing:


The collector current can be no greater than


Which give the following:
mA i
mA i
B FOR
B
3 . 19
09 . 1
2
2
=
=
|
( ) 16 3 . 19 03 . 1 45 . 2 = s + N mA mA N mA
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 48
Fanout Limitations of the TTL
Prototype Example
But computing for v
O
= V
H
, it can be found the the
fanout (N) is 7. Therefore, the max fanout for the
circuit is 7
Part b) analysis - Finding i
IH
and N with
R1
=2

1 5 . 1 ) 75 . 1 )( 2 ( 5
75 . 1
4
7 . 0 8 . 0 5
2
1
= > O
=
|
.
|

\
|

= =
N V mA k N V
and
mA i i
B R IH
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 49
The Standard 7400 Series TTL Inverter
One problem of the TTL inverter prototype
described so far is that the dynamic response is
asymmetrical due to the use of a resistive load to
pull the output up and a BJT to pull the output
down

Another problem is that the fanout capability is
highly sensitive to
R

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 50
The Standard 7400 Series TTL Inverter
The classic approach to fixing these problems is the
implementation of the 7404 hex inverters in a dual-in-line
package (DIP)
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 51
The Standard 7400 Series TTL Inverter
In the 7404 TTL inverter circuit, Q
4
replaces the
passive resistive load pull-up in the prototype TTL
inverter to make it an active pull-up circuit

Q
3
and D
1
ensure that the Q
4
is turned off when Q
2

is on

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 52
Output Analysis of the 7404 Inverter
6 . 3 7 . 0 7 . 0 0 5
1 4 4
= ~
=
OH
D BE C B CC OH
V
v v R i V V
mA i
i i i i i i
where
V V
B
RE B C RE E B
CESAT OL
57 . 2
2
3 3 3 2
2
=
+ = =
=
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 53
Power Consumption of the 7404
mV
P P
P
OH OL
03 . 5
2
=
+
=
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 54
TTL Propagation Delay and Power
Delay Product
The analysis of
propagation delay for
TTL gates is difficult
due to the number of
transistors involved,
so the results can be
approximated
through simulation as
shown
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 55
TTL VTC and Noise Margins
The figure shows the
VTC simulation
results of the TTL
inverter
Using the results
from the simulation
the noise marigns
can be calculates as
V V V NM
V V V NM
H
L
7 . 1 8 . 1 5 . 3
55 . 0 15 . 0 7 . 0
= =
= =
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 56
Fanout Limitations of Standard TTL
The active pull drastically improves the fanout
capabilities of the TTL inverter



However, due to process variations, and the
requirement for the device to operate over a range
of temperatures, N is specified to be less than 10
7 . 72
) 57 . 2 ( 3 . 28 ) 1 (
2
s
s
s
N
mA mA N
i Ni
B FOR IL
|
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 57
Logic Functions in TTL
The basic structure for the TTL NAND gate:
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 58
TTL NAND Gates
The parallel input
can be applied to
create multiple input
NAND gates as seen
in the complete
circuit schematic for
the 7410 three-input
NAND gate
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 59
TTL NAND Gates
One good thing about the multiple input NAND
gate is that it can use a merged transistor structure
to save silicon area since the input BJTs share
their emitters and collectors
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
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Chap 9 - 60
Other TTL Gates
TTL AND-OR-
Invert
Low-power TTL
NAND gate
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 61
Input Clamping Diodes for TTL
From a transient simulation of the TTL inverter, a
negative-going transient can be observed due to
the fast input signal transition

Another source of the transients is from the
distributed L-C interconnection network between
gates causing ringing

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 62
Input Clamping Diodes for TTL
To suppress these transient effects, diodes can be
placed at the input to clamp the signal to ground
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 63
Schottky-Clamped TTL
Since the saturated transistors in TTL gates substantially
slows down the dynamic response of the logic gates, the
Schottky-clamped transistor can be used to help this
problem
The Schottky diode keeps the BJT from going into deep
saturation
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 64
Schottky-Clamped TTL Inverter
Prototype
Replacing the two
BJTs with
Schottky-clamped
transistors, the
Schottky TTL
inverter can be
formed
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 65
Three-Input Schottky TTL NAND Gate
Each saturating transistor
is replaced be a Schottky-
clamped transistor
Q
6
, R
2
, and R
6
replaces R
E

in the original version
which eliminates the first
knee voltage thereby
making the transition
region narrower
Q
5
eliminates the need for
D
1
by providing extra
drive to Q
4

Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 66
Low-Power Schottky TTL
Low-power Schottky TTL
Advanced low-power
Schottky TTL
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 67
ECL and TTL PDP Comparison
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 68
BiCMOS Logic
BiCMOS is a complex processing technology that
provides both NMOS and PMOS, as well as npn
and pnp bipolars

The high impedance input of logic gates (does not
require much to drive them) are provided from the
MOSFETs and high current drive can be provided
from the BJTs due to their high current gain and
transconductance
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 69
BiCMOS Buffers
The CMOS inverter
only has to supply
enough current to
drive the bases of the
BJTs in the BiCMOS
buffer
The BJT stage can
then be designed to
drive the capacitive
load at a certain
speed
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 70
BiCMOS Buffers
The BiCMOS buffers in the figures present two
method to restore the full logic swing at the output
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 71
BiNMOS Buffer
In some BiCMOS
processes, a good npn
might be provided,
but a sub-par pnp is
available, which could
put limitations on
your design
A buffer can be
implemented in the
manner shown in the
figure using only npn
bipolars
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 72
Other BiNMOS Circuits
Full-swing BiNMOS
inverting buffers
BiNMOS buffer using a
single npn bipolar
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 73
BiCMOS Logic Gate
More complex logic gates can also be implemented using
BiCMOS design
Two-input BiCMOS
NOR gate
Two-input BiNMOS
NOR gate
Jaeger/Blalock
10/21/03
Microelectronic Circuit Design
McGraw-Hill
Chap 9 - 74
End of Chapter 9