Jaeger/Blalock

01/05/03
Microelectronic Circuit Design
McGraw-Hill
Chapter12
Operational Amplifier Applications
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Chap 12 - 1
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Chapter Goals
Continue study of methods to determine transfer functions of circuits
containing op amps
Introduction to active filters and switched capacitor circuits
Explore digital-to-analog converter specifications and basic circuit
implementations
Study analog-to-digital converter specifications and implementations
Explore applications of op amps in nonlinear circuits, such as precision
rectifiers
Provide examples of multivibrator circuits employing positive
feedback
Demonstrate use of ac analysis capability of SPICE
Chapter Goals
Chap 12 - 2
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill

Op amp is voltage follower with unity
gain over a wide range of frequencies.
Uses positive feedback through C
1
at
frequencies above dc to realize
complex poles without inductors.
Feedback network provides dc path
for amplifiers input bias currents.
The transfer function is:


A
LP
(s)=
V
o
(s)
V
s
(s)
=
G
1
G
2
C
1
C
2
s
2
+s
G
1
+G
2
C
1
+
G
1
G
2
C
1
C
2
Active Filters: Low-pass
(Transfer Function)
In standard form,

A
LP
(s)=
s
2
s
2
+s
e
o
Q
+e
o
2
e
o
=
1
R
1
R
2
C
1
C
2
Q=
C
1
C
2
R
1
R
2
R
1
+R
2
Often, circuits are designed with
C
1
= C
2
= C.
Chap 12 - 3
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Low-pass
(Frequency Response)
For Q = 0.71, magnitude response is
maximally flat (Butterworth Filter:
Maximum bandwidth without peaking)
For Q >0 .71, response shows undesired
peaking.
For Q < 0.71: Filters bandwidth
capability is wasted.

Sensitivity, represents fractional
change in parameter P due to a given
fractional change in value of Z.
Sensitivity of e
o
with respect to R and
C is:
For e << e
o
, filter has unity gain.
For e >> e
o
, response exhibits
two-pole roll-off at 40dB/decade.
At e = e
o
, gain of filter = Q.
Chap 12 - 4

S
Z
P

S
R
e
o
= S
C
e
o
=
1
2
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Low-pass (Example)
Problem: Design second-order low-pass filter with maximally flat
response.
Given data: f
H
= 5 kHZ
Analysis: C
1
= 2C
2
= 2C and R
1
= R
2
= R.

R=
1
2e
o
C
Q=
1
2
1/e
o
C is the reactance of C at e
o
, R is 30% smaller than this value. Thus
impedance level of filter is set by C. If impedance level is too low, op amp
will not be able to supply current required to drive feedback network.
For a 0.01 F capacitor at 5 kHz,




Final values: R
1
= R
2
= 2.26 kO, C
1
= 0.02 F, C
2
= 0.01 F

1
e
o
C
=
1
10
4
t(10
8
)
=3180 O
R=
3180O
2
=2250 O
Chap 12 - 5
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: High-pass with Gain
(Transfer Function)
Voltage follower in low-pass filter
replaced by non-inverting amplifier
with gain K, which gives an added
degree of freedom in design.
dc paths for both op amp input bias
currents through R
2
and feedback
resistors.


A
HP
(s)=
s
2
s
2
+s
e
o
Q
+e
o
2
e
o
=
1
RC
Q=
R
1
R
2
C
1
+C
2
C
1
C
2
+(1K)
R
2
C
2
R
1
C
1
|
\




|
.
|
|
|
|
1
The transfer function is:
For R
1
= R
2
= R and C
1
= C
2
= C,

e
o
=
1
RC
Q=
1
3-K
For K = 3, Q is infinite; poles are on je
axis causing sinusoidal oscillations.
K > 3 causes instability due to right-
half plane poles.
3 1 s s K
Chap 12 - 6
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: High-pass with Gain
(Frequency Response)
For Q = 0.71, magnitude response is maximally flat (Butterworth Filter
response).
Amplifier gain is constant for e > e
o
, the lower cutoff frequency of
the filter.
Chap 12 - 7
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Band-pass
(Transfer Function)

G
th
V
th
= s C
1
+C
2
|
\

|
.
| +G
th
|
\

|
.
|
V
1
(s)sC
1
V
o
(s)
A
BP
(s)=
V
o
(s)
V
th
(s)
=
R
3
R
1
+R
3
R
2
C
2
R
1
C
1
se
o
s
2
+s
e
o
Q
+e
o
2

e
o
=
1
R
th
R
2
C
1
C
2
Q=
R
2
R
th
C
1
C
2
C
1
+C
2
For C
1
= C
2
= C,


e
o
=
1
C R
th
R
2
Q=
R
2
R
th
BW=
2
R
2
C
Uses inverting op amp and its full loop gain
(ideally infinite).


sC
2
V
1
(s)=
V
o
(s)
R
2
Chap 12 - 8
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Band-pass
(Frequency Response)
Response peaks at e
o
and gain at center frequency is 2Q
2
.
For e << e
o
or e >> e
o
, filter response corresponds to single-pole
high-pass or low-pass filter changing at a rate of 20dB/decade.
Chap 12 - 9
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Tow-Thomas Biquad

T(s)=
a
2
s
2
+a
1
s+a
0
s
2
+s
e
o
Q
+e
o
2
General biquadratic transfer function
to represent low-pass, high-pass,
band-pass, all-pass and notch filters:

In Tow-Thomas biquad, first op amp
is a multi-input integrator and third
op amp is simply an inverter.


V
bp
(s) =
1
sR
1
C
V
s
(s)
1
sRC
-V
lp
(s)
|
\

|
.
|

1
sR
2
C
V
bp
(s)
V
lp
(s) =
1
sRC
V
bp
(s)
A
bp
(s) =K
se
o
s
2
+s
e
o
Q
+e
o
2

K =
R
R
1
e
o
=
1
RC
Q=
R
2
R
BW=
1
R
2
C

A
lp
(s) =K
e
o
2
s
2
+s
e
o
Q
+e
o
2
Thus, center frequency, Q
and gain can each be
adjusted independently.
Chap 12 - 10
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Complete Tow-Thomas
Biquad
The Tow-Thomas Biquad can achieve all filter functions with addition
of extra passive components as shown.

A
v
(s)=
V
o
(s)
V
s
(s)
=
s
2
C
1
C
|
\



|
.
|
|
|
+
s
C
1
R
1

R
3
RR
5
|
\




|
.
|
|
|
|
+
1
RR
4
C
2
s
2
+s
R
R
2
|
\




|
.
|
|
|
|
1
RC
+
1
R
2
C
2
Chap 12 - 11
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Active Filters: Tow-Thomas Biquad
(Example)
Problem: Design band-pass filter using Tow-Thomas circuit
Given data: f
o
= 5 kHZ, BW = 200 Hz, midband gain = 20
Unknowns: R, R
1
,

R
2
,

R
3
, C
Analysis:

Q=
f
o
BW
=10

R=
1
4000tC
=29.4 kO R
2
=10R=294 kO R
1
=
R
2
20
=
R
2
=14.7 kO
Input resistance to the filter is set by R
1
.At the center frequency,

Also, first op amp must supply ac signal current to parallel combination of
R, R
2
,

C. Second op amp must drive parallel combination of R
3
and C.
Third must drive R
3
in parallel with R. If we choose C = 2700 pF,


R
3
can be chosen arbitrarily as long as it doesnt load down second and
third op amps. R
3
= 49.9 kO

X
C
=
1
e
o
C
=R=2R
1
Chap 12 - 12
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Magnitude Scaling
Magnitude of filter impedances may all be increased or decreased by a
magnitude scaling factor K
M
, without changing e
o
or Q of the filter.
To scale the magnitude of the impedance of the filter elements:


Applying magnitude scaling to low-pass filter:

R
'
=K
M
R C
'
=
C
K
M
Z
C
'
=
1
eC'
=K
M
Z
C

e
o
'
=
1
K
M
R
1
K
M
R
2
|
\

|
.
|
C
1
K
M
C
2
K
M
=
1
R
1
R
2
C
1
C
2
=e
o
Q
'
=
C
1
K
M
C
2
K
M
K
M
R
1
K
M
R
2
|
\

|
.
|
K
M
R
1
+K
M
R
2
=
C
1
C
2
R
1
R
2
R
1
+R
2
=Q
Chap 12 - 13
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Frequency Scaling
Cutoff or center frequencies of filter may be scaled by a frequency
scaling factor K
F
without changing Q of the filter if each capacitor
value is divided by K
F
and resistor values are left unchanged.


Applying frequency scaling to low-pass filter:


R
'
= R C
'
=
C
K
F

e
o
'
=
1
R
1
R
2
C
1
K
F
C
2
K
F
=
K
F
R
1
R
2
C
1
C
2
=K
F
e
o
Q
'
=
C
1
K
F
C
2
K
F
R
1
R
2
R
1
+R
2
=
C
1
C
2
R
1
R
2
R
1
+R
2
=Q
Chap 12 - 14
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Switched-Capacitor Circuits
Switched-capacitor (SC) circuits eliminate resistors in filters by
replacing them with capacitors and switches
Resulting filters are discrete-time or sampled-data equivalents of
the continuous-time filters discussed so far
Provide additional flexibility not readily available in continuous-
time form, such as inversion of signal polarity without using an
amplifier
SC circuits are compatible with high density MOS IC processes
SC circuits provide low-pass filters and CMOS ICs for signal
processing and communications applications
Chap 12 - 15
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
SC Integrator
During phase 1, input voltage is sampled and
output is constant. In phase 2, output changes
to reflect sampled information in phase 1.
Charge stored in phase 1 is:

Q
1
=C
1
V
S

V
S
=v
S
n1
( )
T



(

(
Voltage stored on C
1
at
end of sampling interval
Change in charge stored
on C
2
in phase 2.


AQ
2
=C
2
Av
O

Av
O
=
C
1
C
2
V
S

v
O
nT
| |
=v
O
(n1)T
| |

C
1
C
2
v
S
(n1)T
| |
Output voltage at end of nth clock cycle is:
Chap 12 - 16
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Equivalence Between SC Integrator and
Continuous-Time Integrator
Consider total charge Q
s
flowing from source v
S
through resistor R
during clock period T. For simplicity, assume v
S
is constant: v
S
= V
S
.


Equating this charge to charge stored on C
1




f
C
is clock frequency.

For a capacitance of 1 pF and a switching frequency of 100 kHz, the
equivalent resistance is 10 MO, which is much larger than resistors
that can be realized in ICs.

Q
s
=IT=
V
s
R
T
s
V C T
R
s
V
1
=
1
1
1
C
C
f C
T
R = =
Chap 12 - 17
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Noninverting SC Integrator
In phase 1, input voltage is sampled and
output is constant. In phase 2, output
changes to reflect sampled information in
phase 1.



Av
O
=+
C
1
C
2
V
S
Chap 12 - 18
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Stray-Insensitive SC Circuits
In phase 1, source is connected to summing
junction of op amp, charge C
1
V
s
is delivered to
C
2
. Node 1 is driven by and node 2 is kept at
zero.

In phase 2, source is disconnected, output is
constant and C
1
is totally discharged. Any stray
capacitances at nodes 1 or 2 dont introduce
errors into charge transfer process.

Av
O
=
C
1
C
2
V
S
Chap 12 - 19
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Switched-Capacitor Band-Pass Filter

R
th
=
T
C
3
R
2
=
T
C
4
e
o
=
1
T
C
3
C
4
C
1
C
2
= f
C
C
3
C
4
C
1
C
2
Q=
C
3
C
4
C
1
C
2
C
1
+C
2
Center frequency is tunable just by changing
clock frequency, Q is independent of frequency.
But, SC filters are sampled-data systems. Hence,
due to sampling theorem,

f s
f
C
2
Chap 12 - 20
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Switched-Capacitor
Tow-Thomas Biquad
Ability of SC circuits to change polarities without an amplifier
eliminate one op amp in the SC implementation.
Chap 12 - 21
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Digital-to-Analog (D/A) Converters
Fundamentals
In a DAC, an n-bit binary input word (b
1
,b
2
,b
n
) is combined with
reference voltage V
REF
to give output of the DAC.


Full-scale voltage V
FS
is related to V
REF
of the converter by V
FS
= KV
REF

where K determines converter gain commonly set to 1.
V
OS
, the offset voltage of the converter characterizes the DAC output
when the digital input code is zero. Offset voltage is normally adjusted
to zero.
The smallest voltage change at DAC output occurs when the LSB b
n
in
the digital word changes from a 0 to 1 and is also called resolution.

b
1
, the MSB has a weight of one-half V
FS
.

v
O
=V
FS
(b
1
2
1
+b
2
2
2
+...+b
n
2
n
)+V
OS
b
i
e 1,0
}





V
LSB
=2
n
V
FS
Chap 12 - 22
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
D/A Converter Specifications
Offset and Gain Errors
Maximum output of ideal converter is
always 1 LSB smaller than V
FS
.
For shown ideal DAC characteristic,
0.875 V
FS
corresponds to maximum
output code of 111.
Gain error of converter represents
deviation of slope of converter transfer
function from that of corresponding
ideal DAC.
Shown ideal DAC has been calibrated
so that V
OS
= 0 and 1 LSB is V
FS
/8.
Offset voltage is output of converter for
zero binary input code.
Chap 12 - 23
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
D/A Converter Specifications
Linearity Errors
Integral linearity error or linearity
error measures deviation of actual
converter output from straight line fitted
to converter output voltages, specified as
a fraction of LSB.
Overall linearity error is magnitude of
largest error that occurs.Good converter
has linearity error<0.5 LSB
Differential linearity error is
magnitude of maximum difference
between each output step of converter
and ideal step size of 1 LSB.
Integral linearity error for a given binary
input is the sum (integral) of differential
linearity errors for inputs up through the
given input.
Chap 12 - 24
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
D/A Converter Specifications
Monotonicity
If the output of the DAC does not
increase in a monotonic manner if the
input code is increased, the DAC is
said to be non monotonic.

It is possible for a monotonic
converter to have a differential
linearity error >1 LSB but, a non-
monotonic converter always has a
differential linearity error > 1 LSB
Chap 12 - 25
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Weighted-Resistor DAC
Drawbacks:
Need to have accurate resistor
ratios over a wide range of
resistor values.
Switches in series with
resistors require zero offset
voltage and low on-resistance.
Current drawn form reference
varies with input pattern
causing change in voltage drop
in Thvenin equivalent source
resistance of reference leading
to data-dependent errors called
superposition errors.
Binary input data controls the switches.
Successive resistors are progressively
weighted by a factor of 2 producing:

Linearity errors arise due to improper resistor
ratios, op amp offset voltage adds to V
OS
of
converter.


v
O
=V
REF
(b
1
2
1
+b
2
2
2
+...+b
n
2
n
)
Chap 12 - 26
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
R-2R Ladder
Avoids weighted-resistor DAC problem
of wide range of resistor values
Well-suited to IC realization as it
requires matching of only two resistor
values, R and 2R
The contribution of each
bit is reduced by a factor
of 2 going from MSB to
LSB

Drawbacks:
Requires switches with
low on-resistance and zero
offset voltage
Current drawn from
reference varies depending
on input data pattern
Chap 12 - 27
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Inverted R-2R Ladder
Currents in ladder and reference are independent of digital input
Complementary currents are available at output of inverted ladder
Switches still need to have low on-resistance to minimize errors
Chap 12 - 28
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Inherently Monotonic DAC
Analog switch tree connects desired
tap to input of an op amp operating
as a voltage follower.
Each tap on resistor network is
forced to produce voltage greater
than or equal to the taps below it ,
forcing the output to increase
monotonically as the digital input
code increases.
An 8-bit version requires 256
equal-valued resistors, 510 switches
and additional decoding logic.
Chap 12 - 29
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Switched-Capacitor DACs
Since circuits consist only of capacitors
and switches, static power dissipation
occurs only in the op amps.
Dynamic switching losses occur.
When switch changes state, current
impulses charge/discharge network
capacitors, changing voltage on feedback
capacitor by an amount corresponding to
bit weight of switch that changed state.
Circuits represent direct SC analogs of
weighted-resistor and R-2R ladder
DACs. Power consumption is very low.
Chap 12 - 30
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
DACs in Bipolar Technology
Bipolar transistors arent good voltage switches due to their inherent offset voltage in
saturation, but they are very good current sources and switches.
Currents switched into summing junction, supplied through R
F
, determine output voltage of the
DAC.
V
BE
of current-source transistors must be same for proper weighting of current sources,
requiring equal current densities in the transistors. Thus, the area of each transistor is raised by
factor of 2 from LSB to MSB.
Chap 12 - 31
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
DACs in Bipolar Technology (cont.)
Several methods can be used to overcome
problems due to unmanageable transistor and
resistor ratios in bipolar implementations of
DACs - splitting current sources into groups
with proper ladder termination; using an R-2R
ladder to generate weighted current sources;
driving the R-2R ladder by equal-value
current sources.
Chap 12 - 32
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Reference Current Circuitry for Bipolar
Implementations of DACs
An op amp is used to set the current
in the reference transistor.
Bipolar transistor and resistor ratio
matching determine currents in rest
of current-source network.
Chap 12 - 33
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Analog -to-Digital (A/D) Converters
Fundamentals
ADC takes unknown continuous analog input signal, mostly voltage
v
X
and converts it into n-bit binary number, which is a binary fraction
representing ratio between unknown input voltage and full-scale
voltage
For given output code, we know that value of input voltage lies within
a 1-LSB quantization interval.


V
FS
=KV
REF
Quantization error occurs due to
initial underestimation and then
overestimation of input voltage by
output code.
Ideal ADC should pick values of bits
in binary word to minimize
magnitude of quantization error:


v
c
= v
X
(b
1
2
1
+b
2
2
2
+...+b
n
2
n
)V
FS
Chap 12 - 34
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
A/D Converter Specifications
Offset and Gain Errors
Differential linearity error is difference
between actual code step width and ideal
step size of 1 LSB.
ADC with differential linearity error<
1LSB has no missing codes.
Gain error is deviation of slope of
converter transfer function from that of
corresponding ideal ADC.
Shown ADC characteristic has offset
error of 0.5LSB first transition occurs at
a 0.5LSB higher voltage.
Good ADC is monotonic with linearity
error<0.5LSB and no missing codes over
full temperature range.
Integral linearity error or linearity
error is deviation of code transition
points from their ideal positions.
Integral linearity error is sum of
differential linearity errors for individual
steps.

Chap 12 - 35
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
A/D Conversion Techniques
If v
X
> v
REF
, output voltage is high corresponding to logic 1.
If v
X
< v
REF
, output voltage is high corresponding to logic 0.
v
REF
is time-dependent reference voltage, varied till unknown input is
determined within quantization error of converter.

Ideally ADC logic chooses b
i
so that

v
X
V
FS
b
i
2
i
i =1
n
<
V
FS
2
n +1
Chap 12 - 36
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Counting ADC
n-bit DAC used to generate any one of 2
n
outputs
by applying appropriate digital input word. v
X

determined by sequentially comparing it to each
possible DAC output.

Maximum conversion time occurs for full-scale
input signal requiring 2
n
clock periods.
Binary value in counter is smallest DAC voltage
larger than unknown input, not the DAC output
closest to unknown input.
If input varies, binary output is accurate
representation of input signal value at the instant
the comparator changes state.
Requires minimum amount of hardware,
inexpensive to implement.
Chap 12 - 37
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Successive Approximation ADC
Binary search used by SAL to determine v
X
.
n-bit conversion needs n clock periods. Speed limited by
time taken by DAC output to settle within a fraction of an
LSB of V
FS
and by comparator to respond to input signals
differing by small amounts.
Slowly varying input signals not changing by more than
0.5 LSB (V
FS
/2
n+1
) during conversion time (T
T
= nT
C
) are
acceptable.
For a sinusoidal input signal with p-p amplitude V
FS
,


To avoid this frequency limitation, high speed sample-
and-hold circuit is used ahead of the successive
approximation ADC.
Very popular ADC with fast conversion times, used in 8-
to 16- bit converters

f
O
s
f
O
2
n + 2
nt
Chap 12 - 38
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Single-Ramp (Single-Slope) ADC
Reference voltage varies linearly with a well-
defines slope from slightly below 0 to above V
FS
if K= V
FS
/ 2
n
T
C
.
Maximum conversion time occurs for full-scale
input signal requiring 2
n
clock periods.
Counter output is value of v
X
at the time end-
of-conversion signal occurs.
Ramp voltage can be generated using an
integrator connected to a constant reference
voltage.
Dependence of ramps slope on RC product
which is susceptible to changes due to
temperature variations or aging is a limitation of
this ADC.

v
X
=KNT
C

v
X
V
FS
=
N
2
n
Chap 12 - 39
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Dual-Ramp (Dual-Slope) ADC


T
1
=2
n
T
C
T
2
=NT
C
1
RC
v
X
(t)dt
0
T
1
}
=
1
RC
V
REF
(t)dt
T
1
T
1
+ T
2
}

v
X
V
REF
=
T
2
T
1
=
N
2
n
Absolute values of R and C dont affect
operation.
Digital output word gives average value of v
X

during first integration phase.
Conversion time is given by:


Can be used to get resolutions exceeding 20
bits but at lower conversion rates.

T
T
=(2
n
+N)T
C
s2
n +1
T
C
Chap 12 - 40
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Dual-Ramp (Dual-Slope) ADC (cont.)
Integrator in dual-ramp ADC has the
normalized transfer function shown.
Sinusoidal inputs with frequencies that
are exact multiples of 1/T
1
, have
integrals of zero and dont appear at
integrator output. This property is
called normal-mode rejection.
Recent dual-slope ADCs include extra
integration phases for automatic offset
elimination.
Triple ramp ADC uses coarse and fine
down ramps to improve speed by
factor of 2
n/2
for n-bit dual-ramp
converter.
Chap 12 - 41
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Parallel or Flash ADC
Unknown input simultaneously compared to 7
different reference voltages (3-bit converter).
Logic network encodes comparator outputs
into 3-bit binary output representing quantized
value of input voltage.
Very high speed ( up to 10
8
-10
9
conversions/sec) limited only by delays of
comparators and logic network.
Output continuously reflects input delayed by
comparator and logic network.
Requires 2
n
-1 comparators and reference
voltages for n-bit conversion. Used for
resolutions up to 10 bits.
Chap 12 - 42
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Delta Sigma ADCs
Called oversampled because internal
ADC samples integrator output at 16 to
512 times Nyquist rate.Digital filter
produces higher resolution.

V
X
MT
C
RC
|
\


|
.
|
|
V
REF
NT
C
RC
|
\


|
.
|
|
+V
REF
(M N)T
C
RC
|
\


|
.
|
|
=0
V
X
=
V
REF
2
m
|
\


|
.
|
|
(2
m
2N)
If M = 2
m

N/M is average value of binary bit
stream at output.LSB is V
REF=
2
m
Effective resolution is determined by the
time for which the output is averaged.
Converter operation is considerably
complex for time-varying input signals.
Feedback loop attempts to force
integrator output to zero.
Chap 12 - 43
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Delta Sigma ADCs: SC Implementation
Continuous-time integrator can be replaced by
SC integrator for low-power operation.
Charge proportional to input is added to
integrator output at each sample time and
charge given by CV
REF
is added or subtracted
at each sample depending on control sequence
applied to switches.
Delta-Sigma ADCs are inherently linear due
to the 1-bit DAC.
SC integrator suffers less from jitter than
continuous-time integrator as long as the
clock interval is long enough for complete
charge transfer to occur
Chap 12 - 44
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Nonlinear Circuit Applications:
Precision Half-Wave Rectifier
For v
S
> 0, v
O
= v
S
, i > 0, diode is
forward-biased and feedback loop is
closed. Rectification is perfect even for
small input voltages..
For v
S
< 0,diode is cutoff, i = 0, v
O
= 0.
Primary sources of error are gain error
and offset error due to nonideal op amp.
For negative input voltages, output
voltage v
1
is saturated at negative limit.
Large negative voltages across input can
destroy unprotected op amps.
Response time of circuit is slowed down
due to slow recovery of internal circuits
from saturation.
v
O
is rectified replica of v
S

without loss of voltage drop as
in diode rectifier circuit.
Chap 12 - 45
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Nonlinear Circuit Applications: Non-
Saturating Precision Half-Wave Rectifier
For v
S
> 0, v
1
is negative (one diode-
drop below zero), D
2
is forward biased,
current in R
2
is zero, v
O
= 0, D
1
is
reverse biased. Feedback loop is closed
through D
2
.
For v
S
< 0, v
1
is one diode-drop above
output voltage, diode D
1
turns on, D
2
is
off. Circuit behaves as inverting
amplifier with gain - R
2
/ R
1
. Feedback
loop is closed through D
1
and R
2
.
Chap 12 - 46
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Nonlinear Circuit Applications: AC
Voltmeter
Half-wave rectifier is combined
with low-pass filter to form basic
ac voltmeter.
For a sinusoidal input of amplitude
V
M
and frequency e
o
, output is a
rectified sine wave given by its
Fourier series. If cutoff frequency
of low-pass filter e
c
<< e
o
, output
consists primarily of dc voltage
component.


Voltmeter range can be adjusted
through the 4 resistors.

v
O
=
R
4
R
3
R
2
R
1
V
M
t
|
\


|
.
|
|
Chap 12 - 47
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Circuits with Positive Feedback
Comparator
For inputs > V
REF
, output saturates at V
CC
.
For inputs < V
REF
, output saturates at -V
EE
.
Amplifiers built for use as comparators can
handle saturation at the voltage extremes
without incurring excessive internal time
delays.
For noisy inputs, multiple transitions may
occur as input signal crosses reference level.
Chap 12 - 48
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Schmitt Trigger
Schmitt trigger uses positive feedback and
is bistable.
For positive output voltages, V
REF
= |V
CC
.
For negative output voltages, V
REF
= -|V
EE
.
Reference level changes when output
changes state.
Voltage transfer characteristic exhibits
hysteresis and doesnt respond to noise
voltage V
n
magnitude smaller than the
difference between the 2 threshold levels
set by the reference voltage

V
n
<|V
CC
(V
EE
)



(

(
=|(V
CC
+V
EE
)
Chap 12 - 49
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Astable Multivibrator
Uses positive and negative
feedback to generate rectangular
output.
Output voltage switches
periodically between V
CC
and -V
EE
.
For symmetrical power supplies,
output of circuit is square wave with
period T

T =T
1
+T
2
=2RCln
1+|
1|
Chap 12 - 50
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Astable Multivibrator (cont.)
Astable multivibrator can be used to generate square, triangular and
sine wave outputs as shown at frequencies up to few MHz.
Frequency is varied by changing R
3
or C
3.
C
3
is often changed in
decade steps. R
3
may be varied continuously using potentiometer.
Chap 12 - 51
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Monostable Multivibrator or One Shot
Operates with one stable state, generates
single pulse of known duration on application
of trigger signal.
D
1
couples trigger signal into circuit,
clamping diode D
2
limits negative voltage
excursion on capacitor C.
Chap 12 - 52
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
Monostable Multivibrator (cont.)
Output of circuit consists of positive pulse with fixed duration T given by




For well-defined pulse, circuit should not be triggered till voltages on all nodes
return to their quiescent steady-state values.
Recovery time (return of circuit to state before trigger pulse was applied) is
given by:

T =RCln
1+
V
D
V
CC
|
\




|
.
|
|
|
|
1|

T
r
=RCln
1+|
V
CC
V
EE
|
\




|
.
|
|
|
|
1
V
D
V
EE
|
\




|
.
|
|
|
|
Chap 12 - 53
Jaeger/Blalock
01/05/03
Microelectronic Circuit Design
McGraw-Hill
End of Chapter 12
Chap 12 - 54