7/1/03
Microelectronic Circuit Design
McGrawHill
Chapter 15
Multistage Amplifiers
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Chap 15  1
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Chapter Goals
Understand analysis and design of accoupled multistage amplifiers
including voltage gain, input and output resistances and small signal
limitations.
Understand analysis and design of dccoupled multistage amplifiers.
Discuss characteristics of Darlington configuration and cascode
amplifier.
Explore dc and ac properties of differential amplifiers.
Understand basic threestage op amp.
Explore design of classA, classB, classAB output stages.
Discuss characteristics and design of electronic current sources.
Continue understanding the use of SPICE in circuit analysis.
Chap 15  2
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Circuit
Chap 15  3
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Description
MOSFET M
1
operating in CS configuration provides high input
resistance and moderate voltage gain.
BJT Q
2
in CE configuration, the second stage, provides high gain.
BJT Q
3
, an emitterfollower gives low output resistance and buffers the
high gain stage from the relatively low load resistance.
Bias resistors are replaced by
Input and output of overall amplifier is accoupled through capacitors
C
1
and C
6
.
Bypass capacitors C
2
and C
4
are used to get maximum voltage gain
from the two inverting amplifiers.
Interstage coupling capacitors C
3
and C
5
transfer ac signals between
amplifiers but provide isolation at dc, and prevent Qpoints of the
transistors from being affected.
2
1 2
R R
B
R =
4
3 3
R R
B
R =
Chap 15  4
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Equivalent
Circuits
AC
Equivalent
Smallsignal
Equivalent
DC
Equivalent
Chap 15  5
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Input
Resistance and Voltage Gain
598 k 2 . 17 620
1
= =
I
R
k 31 . 4 k 8 . 51 k 7 . 4
2
= =
I
R
232 250 k 3 . 3
3
= =
L
R
M 1 = =
G
R
in
R
4.78 478 S 01 . 0
1 1
1
v
2
v
1
= = = =
L
R
m
g
v
A
k 54 . 3
3
) 1
3
(
3
2
3
2 2
= + +
= =
(
(
L
R
o
r
I
R
in
R
I
R
L
R

t
222 k 54 . 3 mS 8 . 62
2 2
2
v
3
v
2
= =
= =
L
R
m
g
v
A
950 . 0
3
) 1
3
(
3
3
) 1
3
(
3
v
o
v
3
=
+ +
+
= =
L
R
o
r
L
R
o
v
A

t

998
1 2 3
+ =
+
=
in
R
I
R
in
R
v
A
v
A
v
A
v
A
478 2390 598
2
598
2
1 1
= = O = =
t
r
in
R
I
R
L
R
Chap 15  6
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Output
Resistance
3990 54200 4310
2
2 2
x
i
x
v
3
= =
= = =
o
r
I
R
R
CE
out
I
R
th
R
To find output resistance, test
voltage is applied at amplifier
output.
O =
O
+ =
+
+ = = =
+ = + =



.

\






.

\

5 . 60
81
3990
S 0796 . 0
988 . 0
3300
1
3
3
3
3
3300
3
3300
x
i
x
v
3
x
v
3300
x
v
e
i
r
i
x
i
o
th
R
m
g
o
out
R
out
R
out
R

o
Chap 15  7
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Current and
Power Gain
Input current delivered to amplifier from source is
and current delivered to load by amplifier is
i
v
7
10 90 . 9
i
v
i
i
=
+
=
in
R
I
R
s
v 99 . 3
250
s
998v
250
i
v
250
o
v
o
i = = = =
v
A
6
10 03 . 4
i
v
7
10 90 . 9
i
3.99v
i
i
o
i
=
= =
i
A
9
10 02 . 4
6
10 03 . 4 998
i
i
o
i
i
v
o
v
= = = = =
i
A
v
A
s
P
o
P
P
A
Chap 15  8
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Input Signal
Range
For first stage,
For second stage,
For third stage,
On the whole,
V 202 . 0
990 . 0
) 2 1 ( 2 . 0
) ( 2 . 0 =
+
s s
i
v
TN
V
GS
V
1
v
mV 06 . 1
0.990
mV 05 . 1
mV 05 . 1
4.78
0.005 mV 5
mV 5
= s = = s
s = =
i
v
v1
A
1
v
1
v
v1
A
2
v
be2
v
V 7 . 92 005 . 0
) 990 . 0 (
2 1
3 3
1
mV 5
3
3 3
1
)
s
v 990 . 0 (
2 1
3 3
1
3
v
be3
v
=
+
s s
+
=
+
~
v
A
v
A
L
R
m
g
i
v
be
v
L
R
m
g
v
A
v
A
L
R
m
g
V 7 . 92 V) 7 . 92 mV, 06 . 1 mV, 202 min( = s
i
v
mV 5 . 92 V) 7 . 92 ( 998 V) 7 . 92 ( = = s
v
A
o
v
Chap 15  9
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ACcoupled Amplifiers: Methods to
Improve Voltage Gain
Gain of CS amplifier is inversely proportional to square root of drain
current, so voltage gain could be increased by reducing I
D1
while
maintaining a constant voltage drop across R
D1
. Signal range could be
improved by increasing current in output stage and voltage drop across
R
E3
.
Q
1
could be replaced with a FET. This could cause gain loss in third
stage since gain of CD amplifier is typically < that of a CC stage.
However, this loss could be made up by improving gain of first and
second stages.
Chap 15  10
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
CommonEmitter Cascade
To achieve maximum gain, several
CE stages can be cascaded.
For the final stage,
For all other stages,
1 2 3
1  n
v
o
v
...
1
v
2
v
i
v
1
v
v
A
v
A
v
A
v
A = =
CC
V
L
R
mn
g
vn
A 10 ~ =
)
1
(
+
=
i
r
Li
R
mi
g
vi
A
t
If gain is limited by interstage resistances,
each stage has a gain of about 10V
CC
and
overall gain is:
If gain is limited by input resistance of
transistors, it is given by:
Normally as signal and power
levels usually increase in each successive
stage of most amplifiers. Since 
o
< 10V
CC
,
this case often represents the actual limit.
n
CC
V
vn
A


.

\

= 10


.

\


.

\

=
CC
V
on
o o
Cn
I
C
I
n
vn
A 10 ...
3 2
1
1   
1 C
I
Cn
I >
Chap 15  11
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: Circuit
Coupling capacitors in series with signal path
C
1
, C
3
, C
5
, and C
6
are eliminated as they prevent
the amplifier from providing gain at dc or very
low frequencies.
Additional bias resistors in individual stages
are also removed, making design less expensive.
Bypass capacitors C
2
and C
4
affect gain at low frequencies
but dont inherently prevent the
amplifier from operating at dc.
Symmetrical power supplies
are used to set Qpoint voltages
at input and output to about
zero.
Alternating pnp or pchannel
and npn or nchannel transistors
are used from stage to stage to
take maximum advantage of
available power supply voltage.
Chap 15  12
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: DC Analysis
Voltage at drain of M
1
provides base
bias for Q
2
and voltage at collector of
Q
2
provides base bias for Q
3
. All
transistors operate in active region
irrespective of direct connection
between stages.
2
2 1600 5 . 7 ( 0
2
01 . 0
2
2


.

\



.

\



.

\

+ + = =
D
I
TN
V
GS
V
n
K
D
I
So, I
D
= 6.66. mA (which would produce 10.7
V drop across R
S1
and cut off FET) or I
D
=5.29
mA (correct value).
I
B2
<< I
D
,
which is enough to pinch off M
1
.

F2
=150, so I
C2
=1.83 mA and I
B2
= 12.2 A.
I
B3
<< I
C2
,
which < 0.7 V , so Q
2
is in active region.
V 26 . 3 964 . 0 22 . 4
V 22 . 4 620 5 . 7
= =
= ~
DS
V
D
I
D
V
1.84mA
1400
5 . 7
=
O
=
EB2
V
D
V
E2
I
V 82 . 3
V 10 . 1 V 5 . 7 4700
= + =
= ~
C2
V
EB2
V
D1
V
EC2
V
C2
I
C2
V
Chap 15  13
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: DC Analysis
(contd.)
0.4V 0.7V  V 10 . 1 = = =
BE3
V
C2
V
o
V
mA 99 . 3
250 3300
V 5 . 7
=
O
+
O
+
= + =
o
V
o
V
L
I
3
I
E3
I

F3
= 80, so I
C3
=3.94 mA and I
B3
= 49.3 A
V 10 . 7 0.40V  5 . 7 5 . 7 = = =
E3
V
CE3
V
thus Q
3
is in active region.
There is an offset voltage of 0.4 V at output and a nonzero dc current exists in
250 W load resistor. In an ideal design, offset voltage would be zero and no dc
current would appear in load.
Based on Qpoint values, smallsignal parameters can be calculated.
Chap 15  14
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: AC Analysis
Values of interstage capacitors are
higher than those in accoupled
amplifier due to absence of bias
resistors.
Overall characteristics are similar to
those in accoupled amplifier as Q
points and smallsignal parameters of
transistors are similar
Dc coupling requires fewer
components than accoupling
but Qpoints of various stages
become interdependent.
If Qpoint of one stage shifts,
Qpoints of all other stages
might also shift.
Chap 15  15
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: Darlington
Circuit
Darlington circuit behaves similar to
the single transistor but has a current
gain given by the product of current
gains of individual transistors.
DC Analysis: For 
F1
, 
F2
>>1,
V
BE
of composite transistor = 2 diode
voltage drops. So V
CE
>(V
BE1
+ V
BE2
) .
B
I
F2 F1 C2
I
C1
I
C
I   ~ + =
AC Analysis: For the composite transistor,
2 1
2
1
11
'
t

t
r
o
y r ~
=


.

\

0
12
~ y
2 /
2 21
'
m
g y
m
g ~ =
o2
r y
o
r ) 3 / 2 (
1
22
' ~
=


.

\

2 1
0
2
11
21
'
o o
v
y
y
o
   ~
=
=
3 /
2
0
2
1
v
2
v
'
f
i
f
~
=
=
Chap 15  16
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Directcoupled Amplifiers: Cascode
Circuit
Cascode circuit is cascade connection
of CE and CB amplifiers, used in
high gain amplifiers and high output
resistance current sources.
DC Analysis: For a high current gain,
For forwardactive operation of Q
2
,
C1
I
C1
I
F C2
I
C
I ~ = = o
AC Analysis: For the composite transistor,
1
1
11
'
t
t
r y r ~
=


.

\

0
12
~ y
1 21
'
m
g y
m
g ~ =
o2
r
o2
y
o
r  ~
=


.

\

1
22
'
1
0
2
11
21
'
o
v
y
y
o
  ~
=
=
2 2
0
2
1
v
2
v
'
f o
i
f
 ~
=
=
BE
V
BB
V
BE1
V
BE2
V
BB
V
CE1
V 2 > > =
Chap 15  17
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Differential Amplifiers
Differential amplifiers,also considered
the CC/CB cascade, eliminate the
bypass capacitors as well as the
external coupling capacitors at the
input and output of directcoupled
amplifiers.
Each circuit has two inputs.
Differentialmode output
voltage is the voltage
difference between collectors,
drains of the two
transistors.Ground referenced
outputs can also be taken from
collector/drain.
Ideal differential amplifier
uses perfectly matched
transistors.
Chap 15  18
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: DC
Analysis
Both inputs are set to zero,
emitters are connected together.
If transistors are matched,
BE
V
BE2
V
BE1
V = =
C
V
C2
V
C1
V = =
C
I
C2
I
C1
I = =
E
I
E2
I
E1
I = =
B
I
B2
I
B1
I = =
EE
2R
BE
V
EE
V
E
I
=
E
I
F C
I o =
F
C
I
B
I

=
C
R
C
I
CC
V
C2
V
C1
V = =
CE2
V
CE1
V =
V 0 = =
C2
V
C1
V
OD
V
Terminal currents are also equal.
Chap 15  19
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
SmallSignal Transfer Characteristic





.

\






.

\

=
=
T
V 2
id
v
C
I
T
V 2
BE2
v
BE1
v
C
I
C2
I
C1
I tanh 2 tanh 2
The current switch is a digital application of the differential amplifier.
Largesignal transfer characteristic of differential amplifier is given by:
Evenorder distortion terms are eliminated.This increases signalhandling
capability of differential pair. For smallsignal operation, liner term must
be dominant. Hence, we set the thirdorder term to be onetenth the linear
term.







.

\

+


.

\



.

\

+


.

\



.

\

= ...
7
315
17
5
15
2
3
3
1
2
T
V 2
id
v
T
V 2
id
v
T
V 2
id
v
T
V 2
id
v
C
I
mV 27 3 . 0 2 s s
id
v
T
V
id
v
Chap 15  20
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: DC
Analysis (Example)
Problem: Find Qpoints of transistors in the differential amplifier.
Given data: V
CC
=V
EE
=15 V, R
EE
=R
C
=75kO, 
F
=100
Analysis:
A 3 . 95
)
3
10 2(75
V 7 . 0 15
=
O
=

.

\

EE
2R
BE
V
EE
V
E
I
A 4 . 94
101
100
o = = =
E
I
E
I
F C
I
A 944 . 0
100
A 4 . 94

= = =
F
C
I
B
I
V 62 . 8 V) 7 . 0 (  V 92 . 7
V 92 . 7 15
= = =
= =
E
V
C
V
CE
V
C
R
C
I
C
V
Due to symmetry, both
transistors are biased at Q
point (94.4 A, 8.62V)
Chap 15  21
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: AC
Analysis
2
1
id
v
ic
v v + =
2
2
id
v
ic
v v =
Circuit analysis is done by
superposition of differentialmode
and commonmode signal portions.
2 1 c
v
c
v
od
v =
2
2 1 c
v
c
v
oc
v
+
=
(
(
(
(
(
(
(
(
(
(
=
ic
v
id
v
cc
A
cd
A
dc
A
dd
A
oc
v
od
v
A
dd
= differentialmode gain
A
cd
= commonmode to differentialmode
conversion gain
A
cc
= commonmode gain
A
dc
= differential mode to commonmode
conversion gain
For ideal symmetrical amplifier, A
cd
= A
dc
= 0.
Purely differentialmode input gives purely
differentialmode output and vice versa.
(
(
(
(
(
(
(
(
(
=
ic
v
id
v
cc
A
dd
A
oc
v
od
v
0
0
Chap 15  22
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: Differential
mode Gain and Input Resistance
0
e
v 0 ) 2 2 (
e
v
e
v )
4
v
3
v )( (
= = + +
= + +
m
g g
EE
G
EE
G g
m
g
t
t
2
id
v
4
v =
e
v
2
id
v
3
v =
e
v
2
id
v
4
v =
Output signal voltages are:
2
id
v
c1
v
C
R
m
g =
2
id
v
c2
v
C
R
m
g + =
id
v
od
v
C
R
m
g =
2
id
v
3
v =
Emitter node in differential amplifier represents
virtual ground for differentialmode input signals.
Chap 15  23
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: Differential
mode Gain and Input Resistance (contd.)
C
R
m
g
dd
A =
=
=
0
ic
v
id
v
od
v
Differentialmode gain for balanced output, is:
If either v
c1
or v
c2
is used alone as output, output is said to be singleended.
c2
v
c1
v
od
v =
2 2
0
ic
v
id
v
c1
v
1
dd
A
C
R
m
g
dd
A = =
=
=
2 2
0
ic
v
id
v
c2
v
2
dd
A
C
R
m
g
dd
A = =
=
=
Differentialmode input resistance is smallsignal resistance presented to
differentialmode input voltage between the two transistor bases.
If v
id
=0, . For singleended outputs,
t
r
id
R 2
b1
i /
id
v = =
C
R
o
r
C
R
od
R 2 ) ( 2 ~ =
C
R
od
R ~
t
r
) 2 /
id
v (
b1
i =
Chap 15  24
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: Common
mode Gain and Input Resistance
Both arms of differential amplifier are symmetrical.
So terminal currents and collector voltages are equal.
Characteristics of differential pair with common
mode input are similar to those of a CE (or CS)
amplifier with large emitter (or source) resistor.
Output voltages are:
EE
R
o
r ) 1 ( 2
ic
v
b
i
+ +
=

t
ic
v
) 1 ( 2
b
i
c2
v
c1
v
EE
R
o
r
C
R
o
C
R
o
+ +
= = =

t


ic
v
ic
v
) 1 ( 2
) 1 ( 2
b
i ) 1 ( 2
e
v
~
+ +
+
=
+ =
EE
R
o
r
EE
R
o
EE
R
o

t


Chap 15  25
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differential Amplifiers: Common
mode Gain and Input Resistance (contd.)
EE
V
C
V
EE
R
C
R
EE
R
o
r
C
R
o
cc
A
2 2 ) 1 ( 2
0
id
v
ic
v
oc
v
~ ~
+ +
=
=
=

t

Commonmode gain is given by:
For symmetrical power supplies, commonmode gain =0.5. Thus, common
mode output voltage and A
cc
is 0 if R
EE
is infinite. This result is obtained since
output resistances of transistors are neglected. A more accurate expression is:
Therefore, commonmode conversion gain is found to be 0. 0
c2
v
c1
v
od
v = =





.

\

~
EE
R
o
r
o
C
R
cc
A
2
1 1

EE
R
o
r
EE
R
o
r
ic
R ) 1 (
2 2
) 1 ( 2
b
i 2
ic
v
+ + =
+ +
= = 
t

t
Chap 15  26
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
CommonMode Rejection ratio (CMRR)
Represents ability of amplifier to amplify desired differentialmode input
signal and reject undesired commonmode input signal.
For differential output, commonmode gain of balanced amplifier is zero,
CMRR is infinite. For singleended output,
For infinite R
EE
, CMRR is limited by 
o
f
. If term containing R
EE
is
dominant
Thus for differential pair biased by resistor R
EE
, CMRR is limited by
available negative power supply.
Due to mismatches, , gives fractional
mismatch between smallsignal device parameters in the two arms of
differential pair. Hence g
m
R
EE
product is maximized.




.

\

= = =
EE
R
m
g
f
o
cc
A
dd
A
cm
A
dm
A
2
1 1
2
1
2 /
CMRR

EE
V
EE
R
C
I
EE
R
m
g 20 40 CMRR ~ = ~



.

\

A
g
g
EE
R
m
g CMRR
2 1
)
2 1
( 2
g g
g g
g
g
+
=
A
Chap 15  27
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Analysis of Differential Amplifiers
Using HalfCircuits
Halfcircuits are constructed by first drawing
the differential amplifier in a fully
symmetrical form power supplies are split
into two equal halves in parallel, emitter
resistor is separated into two equal resistors in
parallel.
None of the currents or voltages in the circuit
are changed.
For differential mode signals, points on the
line of symmetry are virtual grounds
connected to ground for ac analysis
For commonmode signals, points on line of
symmetry are replaced by open circuits.
Chap 15  28
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Differentialmode Halfcircuits
Applying rules for drawing half
circuits, the two power supply
lines and emitter become ac
grounds. The halfcircuit
represents a CE amplifier stage.
2
id
v
c1
v
C
R
m
g =
2
id
v
c2
v
C
R
m
g + =
id
v
c2
v
c1
v
o
v
C
R
m
g = =
Direct analysis of the halfcircuits yield:
t
r
id
R 2
b1
i /
id
v = =
) ( 2
o
r
C
R
od
R =
Chap 15  29
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Commonmode Halfcircuits
All points on line of symmetry become open circuits.
DC circuit with V
IC
set to zero is used to find amplifiers Qpoint.
Last circuit is used for for commonmode signal analysis and
represents the CE amplifier with emitter resistor 2R
EE
.
Chap 15  30
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Commonmode Input Voltage
Range
For symmetrical power supplies, V
EE
>> V
BE
, and R
C
= R
EE
,
EE
R 2
C
R
F
CC
V
BE
V
EE
V
EE
R 2
C
R
F
CC
V
IC
V
EE
R
EE
V
BE
V
IC
V
F C
I
IC
V
C
R
C
I
CC
V
CB
V
o
o
o
+
s
+
s
> =


.

\

1
1
2
0
3
CC
V
IC
V s
Chap 15  31
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Biasing with Electronic Current Sources
Differential amplifiers are biased using electronic
current sources to stabilize the operating point and
increase effective value of R
EE
to improve CMRR
Electronic current source has a Qpoint current of I
SS
and an output resistance of R
SS
as shown.
DC model of the electronic current source is a dc
current source, I
SS
while ac model is a resistance R
SS
.
SPICE model includes both ac
and dc models.
SS
R
0
V
SS
I
DC
I =
Chap 15  32
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
MOSFET Differential Amplifiers: DC
Analysis
Op amps with MOSFET inputs have a
high input resistance and much higher
slew rate that those with bipolar input
stages.
Using halfcircuit analysis method, we
see that I
S
= I
SS
/2.
n
K
SS
I
TN
V
n
K
D
2I
TN
V
GS
V
TN
V
GS
V
n
K
D
I
+ = + =
=


.

\

2
2
D
R
D
I
DD
V
D2
V
D1
V = = 0
o
V =
and
GS
V
D
R
D
I
DD
V
S
V
D
V
DS
V + = =
Chap 15  33
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
SmallSignal Transfer Characteristic
MOS differential amplifier gives improved linear input signal range and
distortion characteristics over that of a single transistor.
Secondorder distortion product is eliminated and distortion is greatly
reduced. However some distortion prevails as MOSFETs are nor perfect
square law devices and some distortion arises through voltage dependence
of output impedances of the transistors.
( ) ( )
(
(
=
2 2
2
TN
V
GS2
v
TN
V
GS1
v
n
K
D2
I
D1
I
2
id
v
GS
V
GS2
v =
For symmetrical differential amplifier with purely differentialmode input
2
id
v
GS
V
GS1
v + =
id
v
m
g
id
v
TN
V
GS
V
n
K
D2
I
D1
I = =


.

\

Chap 15  34
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
MOSFET Differential Amplifiers: DC
Analysis (Example)
Problem: Find Qpoints of transistors in the differential amplifier.
Given data: V
DD
=V
SS
=12 V, I
SS
=200 A, R
SS
= 500 kO, R
D
= 62 kO,
= 0.0133 V
1
, K
n
= 5 mA/ V
2
, V
TN
=1V
Analysis:
A 100 = =
2
SS
I
D
I
V 8 . 6 = + s
s =


.

\

TN
V
D
R
D
I 
DD
V
IC
V
TN
V
D
R
D
I 
DD
V 
IC
V
GD
V
V 20 . 1
2
5mA/V
A 200
1 = + =
GS
V
V 7 V 2 . 1 ) A)(62k 100 (  V 12 = + O =
DS
V
To maintain pinchoff operation of M
1
for nonzero V
IC
,
Chap 15  35
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
MOSFET Differential Amplifiers:
Differentialmode Input Signals
2
id
v
d1
v
D
R
m
g =
2
id
v
d2
v
D
R
m
g + =
id
v
od
v
D
R
m
g =
Source node in differential amplifier represents virtual ground
Differentialmode gain for balanced output is
Gain for singleended output is
D
R
m
g
dd
A =
=
=
0
ic
v
id
v
od
v
2 2
0
ic
v
id
v
d1
v
1
dd
A
D
R
m
g
dd
A = =
=
=
2 2
0
ic
v
id
v
d2
v
2
dd
A
D
R
m
g
dd
A = + =
=
=
=
id
R
D
R
od
R 2 =
Chap 15  36
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
MOSFET Differential Amplifiers:
Commonmode Input Signals
Electronic current source is modeled by twice its small
signal output resistance representing output resistance of the
current source.
Commonmode halfcircuit is similar to inverting amplifier
with 2R
SS
as source resistor.
ic
v
2 1
d2
v
d1
v
SS
R
m
g
D
R
m
g
+
= =
ic
v
ic
v
2 1
2
s
v ~
+
=
SS
R
m
g
SS
R
m
g
0
d2
v
d1
v
od
v = = Thus, commonmode conversion gain= 0
SS
R
D
R
SS
R
m
g
D
R
m
g
cc
A
2 2 1
0
id
v
ic
v
oc
v
~
+
=
=
=
Due to infinite current gain of
FET, r
o
can be neglected.
=
ic
R
Chap 15  37
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
CommonMode Rejection ratio (CMRR)
For purely commonmode input signal, output of balanced MOS amplifier
is zero, CMRR is infinite. For singleended output,
R
SS
(which is much > R
EE
and thus provides more Qpoint stability) should
be maximized.
To compare MOS amplifier directly to BJT amplifier, assume that MOS
amplifier is biased by
From given data in example, MOS amplifiers CMRR=54 or 35 dB (almost
10 dB worse than BJT amplifier).To increase CMRR in BJT and FET
amplifiers, current sources with higher R
SS
or R
EE
are used.
SS
R
m
g
SS
R
D
R
D
R
m
g
cc
A
dd
A
cm
A
dm
A
=
= = =
) 2 /(
2 / ) (
2 /
CMRR
SS
I
GS
V
SS
V
SS
R
=
TN
V
GS
V
GS
V
SS
V
TN
V
GS
V
SS
R
SS
I
TN
V
GS
V
SS
R
D
I
=
) ( 2
CMRR
Chap 15  38
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twoport model for Differential
Amplifiers
Twoport model simplifies circuit analysis of differential amplifiers.
Expressions for FET are obtained by substituting R
SS
for R
EE
.
EE
R
f
oc
R
o
r
od
R
EE
R
cm
v
cm
v
EE
R
m
g
m
g
cm
i
dm
v
m
g
dm
i
2
2
2 2 1
~
=
~
+
=
=
Chap 15  39
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Differential Amplifier Design (Example)
Problem: Find Qpoints of transistors in the differential amplifier.
Given data: A
dm
=40 dB, R
id
>250 kO, singleended CMRR> 80 dB, V
IC
at least 5V, MOSFETs with: = 0.0133 V
1
, K
n
= 50 A/ V
2
, V
TN
=1V,
BJTs with : 
F
=100, V
A
=75V, I
S
=0.5 fA
Assumptions: Activeregion operation, symmetrical power supplies, 
o
=

F
, v
id
maximum of 30 mV.
Analysis:
A
dm
=40 dB =100. To achieve this gain with resistively loaded amplifier, we
use BJT. For A
dm
= g
m
R
C
=40 I
C
R
C
, required gain can be obtained with
voltage drop of 2.5 V across R
C
.
For bipolar differential amplifier, R
id
=2r
t
, so, r
t
=125 kO.
A 20 = s
t

r
T
V
o
C
I
Chap 15  40
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Differential Amplifier Design (Example
contd.)
Choose I
C
= 15 A to provide safety margin. So R
C
=2.5 V/15 A =167 kO.
Choose R
C
= 180 kO as the nearest value with 5% toleranceand alos to
compensate for neglecting r
o
in the analysis.
V
IC
of 5V requires collector voltage to be at least 5 V at all times. We also
know that v
id
can be a maximum of 30 mV for linearity. So ac
component of differential output will not be greater than 100(0.03 V)=3V,
half of which appears at each collector. Thus dc signal across R
C
wont
exceed 4 V( 2.5 V dc + 1.5 V ac) and positive power supply must fulfill
Choose V
CC
=10 V to dive desired margin of 1 V, For symmetrical supplies,
V
EE
= 10 V. Singleended CMRR of 80 dB needs
Choose current source with I
EE
=30 A and R
EE
> 20 MO
V 9 4)V 5 ( V 4 = + = + >
IC
V
CC
V
M 7 . 16
) A 15 )( V / 40 (
4
10 CMRR
= = >
m
g
EE
R
Chap 15  41
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twostage Prototype of an Op Amp
For higher gain, pnp CE amplifier is
connected at output of the input stage
differential amplifier.
Virtual ground at emitter node allows input
stage to achieve full inverting amplifier
gain without needing emitter bypass
capacitor.
Pnp transistor permits direct coupling
between stages, allows emitter of pnp to be
connected to ac ground and provides
required voltage level shift to bring output
back to zero.
Bypass and coupling capacitors are thus
eliminated.
Differential amplifier provides
desired differential input,CMRR
and ground referenced output as
the input stage of op amp.
Chap 15  42
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twostage Op Amp: DC Analysis
This circuit requires a resistance in
series with emitter of Q
3
to stabilize Q
point (as collector current of Q
3
is
exponentially dependent on base
emitter voltage), at the expense of
voltage gain loss.
From dc equivalent circuit, I
E1=
I
E2
= I
1
/2. If
base current of Q
3
is neglected and CB
current gains are one,
As both inputs are zero, output also=0
I
S3
is saturation current. For zero offset voltage
BE
V
C
R
1
I
CC
V
CE2
V
CE1
V + ~ ~
2
R
EE
V
C3
I / =
CC
V
EC3
V
=





.

\

+
=
S3
I
C3
I
T
V
EB3
V 1 ln





.

\






.

\

+
=
S3
I
C3
I
F3
C3
I
2
1
I
F
T
V
C
R 1 ln
2

o
Chap 15  43
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twostage Op Amp: AC Analysis
(Differential Mode)
Halfcircuit can be constructed from ac
equivalent circuit in spite of asymmetricity, as
voltage variations at collector of Q
2
dont
substantially alter transistor current in
forwardactive operation region.
From smallsignal circuit model,
R
m
g
vt
A
r
C
R
m
g
L
R
m
g
vt
A
3
c2
v
o
v
2
)
3
(
2
2
1
2
2
id
v
c2
v
1
= =
= = =
t
Chap 15  44
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twostage Op Amp: AC Analysis
(Differential Mode contd.)
This can be rewritten as
Base current of Q
3
is neglected so, I
C2
R
C
=V
BE3
=0.7 V, I
C3
R=V
EE
,
3
3
2
2
)
3
)(
3
(
2
2
2 1
c2
v
o
v
id
v
c2
v
id
v
o
v
t

t
r
C
R
R
o C
R
m
g
R
m
g r
C
R
m
g
vt
A
vt
A
dm
A
+
= = = = =
3 2
2
3
40
3
40
3 2
40
2
1
3 3
3 3 2
2
1
o C
R
C
I
C
I
C
I
R
C
I
o C
R
C
I
o C
R
m
g
R
m
g R
o C
R
m
g
dm
A




+
=
+
=


.

\



.

\



.

\



.

\






.

\

+
=
2
3
3
28
1
560
C
I
C
I
o
EE
V
dm
A

Upper limit onI
C2
and I
1
is set by maximum dc bias
current at input, lower limit on I
C3
is set by minimum
current to drive total load impedance at output.
1
2
2
2
id
i /
id
v
t t
r r
id
R = = =
R
o
r R
out
R ~ =
3
Chap 15  45
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Twostage Op Amp: AC Analysis
(Common Mode)
From ac equivalent circuit, we
observe that circuitry beyond
collector of Q
2
is same as that in
differential mode halfcircuit.
The difference in collector
currents causes difference in
output voltage.
1 2
2 1
ic
v
2
1
2
2
2 1
ic
v
2
1
) 1
2
( 2
2
ic
v
2
c2
i
R
m
g
m
g
R
o
m
g
m
g
R
o
r
o
+
~
+
=
+ +
=
o

t

From ac equivalent circuit for common
mode inputs,
For differentialmode inputs, collector
current was
Thus,
id
v
2
2
c2
i
m
g
=
1 2
2
1 2
2 1
CMRR
1 2
2 1
2
3
3
1 2
2 1
2
R
m
g
R
m
g
cm
A
dm
A
R
m
g
dm
A
r
C
R
R
o
R
m
g
C
R
m
g
~
+
= =
+
=
+ +
t

Chap 15  46
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Improving Op Amp Voltage Gain
Overall amplifier gain decreases rapidly as the
quiescent current of second stage decreases.
Voltage gain can improve if resistor in second
stage is replaced by current source with R
2
>>
r
o3
, if R
2
is neglected,
This expression can be reduced to
)
3 3
)(
3
(
2
2
2 1 o
r
m
g r
C
R
m
g
vt
A
vt
A
dm
A = =
t





.

\

+
~
2
3
3
28
1
3
560
C
I
C
I
o
A
V
dm
A

3
3
2 o
r
o
r R
out
R ~ =
Output resistance is degraded, amplifier more represents
transconductance amplifier than a true low output
resistance voltage amplifier.
Chap 15  47
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Reducing Output Resistance
A CC stage is added to the
prototype to maintain voltage
gain but reduce output
resistance.
From ac equivalent circuit,
1
) 1
4
(
4
) 1
4
(
3
)
3
(
3 2
)
3
(
2
2
1
~
+ +
+
=
=
=
L
R
o
r
L
R
o
v
A
R
CC
in o
r
m
g
v
A
r
C
R
m
g
v
A

t

t
L
R
o
r
R
CC
in
) 1
4
(
4
+ + = 
t
2
2
t
r
id
R =





.

\

+
+ =
+
+ =
+
+ =
3
4
1
4
3
1
4
1
1
4
3
4
1
1
4
4
4
1
C
I
C
I
o
f
m
g
o
o
r
m
g
o
th
R
m
g
out
R

 
3 2 1
3
v
o
v
2
v
3
v
id
v
2
v
vt
A
vt
A
vt
A
dm
A = =
Chap 15  48
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ThreeStage Bipolar Op Amp Analysis
Problem: Find differentialmode gain, CMRR, input and output resistances.
Given data: V
CC
=V
EE
=15 V, 
o1
= 
o2
= 
o3
= 
o4
=100, V
A3
=75V, I
1
= 100
A, I
2
= 500 A, I
3
= 5 mA, R
1
= 750 kO , R
L
= 2 kO, R
2
and R
3
are infinite.
Analysis:
O = =
= =
=
+
+ =
+
+ = + =
= = =
k 55 . 4
S
2
10 2 . 2 40
A 550
1 1
mS 98 . 1 ) ( 40 40
m3
g
o3
3
r
C3
I
m3
g
F4
3
I
2
I
F4
E4
I
2
I
B4
I
2
I
C3
I
E2
I
F2 C2
I
m2
g

t
 
o
Voltage at node 3 is one baseemitter voltage
drop above zero. V
EC3
=150.7=14.3 V.
Chap 15  49
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ThreeStage Bipolar Op Amp Analysis
(contd.)
O =
=
O = =
= =
O =
+
=
k 9 . 15
505
4
mA 95 . 4
k 162
F3
C3
I
C2
I
EB3
V
C
R
C4
I
T
V
o4
r
E4
I
F4 C4
I
C3
I
EC3
V
A3
V
3 o
r


t
o
1 998 . 0
) 1
4
(
4
) 1
4
(
3
1980 ) ) 1
4
(
4
(
3
3 2
50 . 3 )
3
(
2
2
1
~ =
+ +
+
=
= + + =
= =


.

\

L
R
o
r
L
R
o
v
A
L
R
o
r
o
r
m
g
v
A
r
C
R
m
g
v
A

t


t
t
6920
3 2 1
= =
vt
A
vt
A
vt
A
dm
A
k 101
2
2 = =
t
r
id
R
k 61 . 1
1
4
3
4
1
=
+
+ =
o
o
r
m
g
out
R

63.5dB 1490
1 2
CMRR = = = R
m
g
Overall gain is lower because of lower gain of first stage (since r
t3
<< R
C
) and
lower gain than expected for second stage (as reflected loading of R
L
is of same
order as r
o3
).
Chap 15  50
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
CMOS Op Amp Prototype: Circuit
Differential amplifier (M
1
and
M
2
) followed by CS stage M
3
and source follower M
4
.
Current sources are used to
bias differential input and
source follower stages and as
load for M
3
.
Chap 15  51
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
CMOS Op Amp Prototype: AC Analysis





.

\




.

\

+
=
= =
L
R
m
g
L
R
m
g
D
R
m
g
f
vt
A
vt
A
vt
A
dm
A
4
1
4
2
2
3
3 2 1
\






.

\

=
= =
3
3
3
2
3
3
2
2
3
1
2 2
3
3
) 1 (
2 1
TP
V
p
K
D
I
D
I
p
K
D
I
n
K
TN
V
GS
V
GS
V
f vt
A
vt
A
dm
A
\

=
TN
V
GG
V
n
K
D
I





.

\

=
T
V
B
R
B
I
S
I
C
I
2
exp
Chap 15  57
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ClassAB Output Stages for Op Amps
Chap 15  58
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
ShortCircuit Protection
High current, high power dissipation or direct destruction
of baseemitter junction can destroy the BJT if output of a
follower circuit is accidentally shorted to ground. Q
2
is
added to protect the emitter follower.
Normally, voltage across R is <0.7 V, Q
2
is cutoff. Q
2
turns
on to shunt extra current away from base of Q
1
. I
E1
is
limited to
For complementary output stage, similar
currentlimiting circuitry is used. In
MOSFET complementary output stages,
output current is limited to
R R
BE
V
E1
I / 7 . 0 /
2
= =
R
n
K
G
I
TN
V
R
GS
V
S1
I
2
/ 2
2 2
+
= =
Chap 15  59
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Transformer Coupling: Follower
Transformer coupling is used in
amplifiers to achieve high voltage gain
and efficiency while delivering power
to low impedance loads.
Coupling capacitor blocks dc path
through primary of transformer.
2
v
1
v n =
1
i
2
i n =
L
Z n Z
2
1
=
Transformer provides impedance
transformation by n
2
. From ac
equivalent circuit,transistor must
drive
Transformer restricts operation to
frequencies >dc.
L
R n
EQ
R
2
=
n
1
v
o
v =
Chap 15  60
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Transformer Coupling: Inverting
Amplifier and ClassB Output Stage
At dc, transformer is a short circuit,
quiescent operating current is supplied
through transformer primary. At signal
frequency load n
2
R
L
is presented to
transistor.
Inductance permits signal voltage to swing
symmetrically above and below V
DD
.
As both quiescent
operating currents
= 0, emitters can be
directly connected
to transformer
primary.
Chap 15  61
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Electronic Current Sources: Introduction
Current through ideal current
source is independent of voltage
across its terminals and the output
resistance is infinite.
In electronic current sources,
current depends on voltage across
the terminals and they have a
finite output resistance.
Current
source
Current
sink
Singletransistor current sources operate in only one quadrant of iv space but
realize very high output resistances.
Chap 15  62
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Current Sources: Figure of Merit
is used as a figure of merit for comparing different current sources.
For a given Qpoint current, V
CS
represents the equivalent voltage that
will be needed across a resistor to achieve same output resistance as
given current source.
For resistor:
For BJT:
For MOSFET:
out
R
o
I
CS
V =
1 1
1
~ + =
+
= = =
~ + =
+
= = =
= = =
DS
V
D
I
DS
V
D
I
o
r
D
I
out
R
o
I
CS
V
A
V
CE
V
A
V
C
I
CE
V
A
V
C
I
o
r
C
I
out
R
o
I
CS
V
EE
V R
R
EE
V
out
R
o
I
CS
V
Chap 15  63
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Higher Output Resistance Sources
Output resistance of the current source
can be increased by placing a resistor
in series with the emitter or source of
the transistor.
For BJT:
A
V
o
CE
V
A
V
o
CS
V
A
V
o
CE
V
A
V
o
CS
V
E
R r R R
E
R
o
o
r
out
R
   
t

~ + = ~ + =
+ +
+ =






.

\

) ( ) (
2 1
1
For MOSFET:
3
) 1 (
SS
V
f CS
V
S
R
f S
R
m
g
o
r
out
R
~
~ + =
Chap 15  64
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Multiple Output Current Sources
O =
+
=
=
+
=
k 39 . 3
2 1
2 1
V 18 . 3
2 1
1
R R
R R
BB
R
SS
V
R R
R
BB
V



.

\

O
+
O
+
O
+
+
= + +
k 47 . 0
1
k 7 . 4
1
k 22
1
1
1
15 ) 7 . 0 (
3 2 1
F
B
V
B
I
B
I
B
I

7 . 0 = =
B
V
BE
V
B
V
E
V
Assume equal current gains for all BJTs.
A 484
2 2
A 103
k 22
15
1 1
V 7 . 12 7 . 0 12
V 12 ) 3390 )(
3 2 1
( 18 . 3 15
= =
=
+
= =
= =
= + + + =
B
I
F C
I
E
V
F B
I
F C
I
E
V
B
I
B
I
B
I
B
V

o 
mA 84 . 4
3 3
= =
B
I
F C
I 
Chap 15  65
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Multiple Output Current Sources (contd.)
Output resistances of the three current sources are given by:
k 177
3
M 48 . 5
2
M 8 . 31
1
2 1
1
100
1
7 . 72
2 1
1
1
=
=
=
+
+
+ =
+
+
+ =
(
(
(
(
(
(
(
(
(
(
(











.

\

out
R
out
R
out
R
E
R
r R R
C
I
E
R
r R R
o
o
r
out
R
t t

Chap 15  66
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Transistor Current Source
Design Example
Problem: Design a current source with the largest possible output
voltage range that meets the given output resistance specification.
Given data:V
EE
= 15 V, I
o
= 200 A, I
EE
< 250 A, R
out
> 2 MO, BJTs
available with (
o
, V
A
) = (80, 100 V) and (150, 75 V), V
B
must be as low
as possible.
Assumptions: Active region and smallsignal operating conditions. V
BE
= 0.7 V, V
T
= 0.025 V, choose V
o
= 0 V as representative output value.
Analysis:
V 2000 ) M 10 )( A 200 (
2 1
1
= > =
s =
s
+ +
+ =






.

\

out
R
o
I
A
V
o
A
V
o
out
R
o
I
CS
V
o
r
o
E
R r R R
E
R
o
o
r
out
R



t

Chap 15  67
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Transistor Current Source
Design Example (contd.)
Both BJTs can satisfy these conditions. But, we choose BJT (150, 75V)
with higher 
o
V
A
product.
Total current < 250 A. As output current is 200
A, maximum of 50 A can be used by base bias
network. Current used by base bias network must
be 5 to 10 times base current of BJT (1.33 A for
BJT with a current gain of 150). So bias network
current =20 A.
Large R
BB
reduces output resistance and output
compliance range (increase V
BB
).Trading
increased operating current for wider compliance
range, choose bias network current of 40 A.
O = ~ + k 375
A 40
V 15
2 1
R R
Chap 15  68
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Transistor Current Source
Design Example (contd.)
Following set of equations can be used in a spreadsheet analysis to
determine design variables. Primary design variable is V
BB
which can
be used to determine other variables.
F
o
I
B
I

=




.

\

O = + =
15
k 375
15
)
2 1
(
1
BB
V
BB
V
R R R
1
k 375
1
)
2 1
(
2
R R R R R O = + =
2
1
R R
BB
R =




.

\

=
o
I
BB
R
B
I
BE
V
BB
V
F E
R o
) (
BB
R
B
I
BE
V
BB
V
EE
V
CE
V =
o
I
T
V
o
r

t
=
o
I
CE
V
A
V
o
r
+
=






.

\

+ +
+ =
E
R r R R
E
R
o
o
r
out
R
t

2 1
1
Chap 15  69
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGrawHill
Bipolar Transistor Current Source
Design Example (contd.)
From spreadsheet, smallest V
BB
for which output resistance > 10MO with
some safety margin is 4.5 V, resulting output resistance is 10.7MO.
Analysis of circuit with 1% resistor values gives I
o
= 200 A and supply
current = 244 A.
Final current source design is as shown.
MOSFET current source design can also be analyzed in similar manner.
Chap 15  70
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