By Anindita Dash

Introduction Need Process

Difficulty
Tools And Techniques

Conclusion
References

The analog CMOS integrated circuit synthesis process consists of three steps.
Topology Selection

Circuit Sizing
Design Verification

Analog circuit synthesis is a design optimization problem containing two parts.

Topology Selection

Transistor Sizing

Synthesis system requires two types of problem solving knowledge.

Declarative

Control

Multi placement Structures for fast and optimized placement in analog circuit synthesis.
Optimization Based(On sized circuit)
Simulation based and use genetic algorithm to meet the specified performance constraints. Takes more time for algorithm search

Template Based(On un-sized circuit)

Layout inclusive sizing process. Reduced time for algorithm search

Parallel on Analog Circuit Synthesis.

Problem Partitioning Techniques is used.
Functionality analysis based circuit partitioning Performance specification decomposition Generation of test bench performance evaluation

Speed is improved. Computing efficiency is improved. Multi-threading is used. Adaptive task scheduler and/or MPI based task scheduler is used.

The Sizing Rules Method for CMOS Analog Integrated Circuit Synthesis.

Topology Synthesis of Analog Circuits with yield optimization and evaluation using Pareto Fronts(2011)

Differential Evolution and Swarm Intelligence techniques for Analog Circuit Synthesis. Based on evolutionary optimization of ANFIS Space Mapped Model(2008) Anaconda: Simulation-based synthesis of Analog Circuits via stochastic Pattern Search.
Abstract Model Of Analog Synthesis

An Analog Performance estimator for improving the effectiveness of CMOS Analog System circuit Synthesis(VHDL -AMS)

Knowledge Based Encode the circuit behavior in memory. Tools: OASYS(Generate and simulate approach) IDAC Optimization Based Obtain the circuit behavior via simulation. Tools: OPASYN(selects a circuit by relating the topology structures to performance specification) STAIC(successive solution refinement methodology) DELIGHT.SPICE KOAN/ANAGRAM(Placement Tools)

Algorithm Based Uses mathematical calculation for circuit behavior estimation. ARIADNE(symbolic simulation based) DARWIN(depends on basic blocks) DONALD(works on system design equation ) FASY(fuzzy logic based which selects topology from a predefined library) ASTRX/OBLX(automated synthesis tool , circuit topology already selected) LAYLA(placement algorithm using genetic)

From every corner of the world researchers trying to improve the synthesis technique for analog circuit based on time , complexity , area and efficiency. Some are proposed and some are accepted. Not satisfactory result till today. Still an ongoing research topic

Automated Synthesis of Analog Electrical Circuits by Means of Genetic Programming John R. Koza , Member, IEEE, Forrest H Bennett, III, Associate Member, IEEE , David Andre, Martin A. Keane, Member, IEEE, and Frank Dunlap, Member, IEEE Techniques for Synthesis of Analog Integrated Circuits Topology Synthesis of Analog Circuits with Yield Optimization and Evaluation using Pareto Fronts Oliver Mitea, Markus Meissner, Lars Hedrich Electronic Design Methodology, Department of Computer Science, University of Frankfurt/Main, Germany{mitea , meissner , hedrich}@em.cs.uni-frankfurt.de Fast Synthesis of Analog Circuits Based on Evolutionary Optimization of ANFIS Space Mapped Model Vahid Asadpour Electrical Engineering Faculty Sadjad University Mashad, IRAN Email: asadpour@aut.ac.ir Differential Evolution and Swarm Intelligence techniques for Analog Circuit Synthesis

Parallel on Analog Circuit Synthesis ,Yuping Wu Lan Chen TianchunYe Institute of Microelectronics of CAS Beijing, P.R. of China Email: {wuyuping, chenlan, yetianchun}@ime.ac.cn A novel real-coded scheme for evolutionary analog circuit synthesis, Jingsong He Department of Electronic Science and Technology ,University of Science and Technology of China Hefei, China hjss@ustc.edu.cn The roIe of designer knowledge for circuit-level optimization within an analog synthesis system D.Enright, R.J.Mack, & R.E.Massara ,Department of Electronic Systems Engineering ,University of Essex, UK Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis , Raoul F. Badaoui and Ranga Vemuri