Overview:
Introduction/Circuit Protection Voltage Transients - Emphasis on ESD ESD Suppression Technologies Usage of ESD Suppressors - In Applications Board Layout Considerations
CIRCUIT PROTECTION
OVERCURRENT PROTECTION
OVERVOLTAGE PROTECTION
Power Input
Power Source
Fault Current
Fuse/PTC
Circuitry
ESD Suppressor
Signal Input
A sudden change in the electrical condition of any circuit will cause a transient voltage to be generated from the energy stored in circuit capacitance and inductance. Effective transient overvoltage protection requires that the impulse energy be dissipated in the added suppressor at a voltage low enough to ensure survival of the circuit components.
ESD (Electro-Static Discharge) Lightning Strike Inductive Load Switching Commutative Spikes Automotive Load Dump
75% of field equipment failure are caused by Electrical Over-Stress (EOS)!!! Semiconductor devices are becoming increasingly Intolerant to voltage transients
A Lightning strike several miles away can induce transients in your equipment
Power distribution transformers susceptibility impacts clean power condition ESD failures can occur in CMOS at 2kV common, where as most EOS occurrences are at 8kV or higher
AUTOMOTIVE ISO 7637 GM 9105 LOAD DUMP PROTECTION OF INDUCTIVE LOADS TRANSIENT BURSTS
Suppression
WHITE GOODS
INDUSTRIAL PANELS
Pass is achieved if system suffers no upset or damage 10 pulses are applied to the Device Under Test, in the polarity that the DUT is most sensitive to
Discharge Voltage
2 kV 4 kV 6 kV 8 kV
Initial Current
7.5 A 15.0 A 22.5 A 30.0 A
30 ns 60 ns Current Current
4A 8A 12A 16A 2A 4A 6A 8A
Current (A)
60 ns
Time (ns)
35,000 V
1,500 V
12,000 V
250 V
Worker at bench
6,000 V
100 V
7,000 V
600 V
18,000 V
1,500 V
ESD ACCOUNTS FOR 30% OF ALL FIELD FAILURES DEMANDING NEW STANDARDS LIMITATIONS OF EXISTING DEVICES
SOFT FAILURE: Data corruption or system latch up. Reboot resolves the latch up temporary problem.
LATENT DAMAGE: IC still functional, but affected component will degrade with time or have shortened life span.
CATASTROPHIC FAILURE: Permanent damage done to structures within integrated circuitry (transistors and interconnects). Junction Burnout Oxide Punch-through Melted Trace
Oxide Punch-through
Transistors
Si
Dielectrics
Metallization Burnout
Al SiO2
Si
Interconnects
Parametric degradation
Clamping Devices
Transient Event Vline Vline Energy Dissipated Clamp Voltage
Crowbar Devices
Transient Event Vline Vline Reset Time
Trigger Voltage
Multilayer Suppressors (ML, MLE, AUML) Surface mount chip devices for Surge protection / ESD protection Diode/SCR Array (SP 72X) - Avalanche Arrays (SP05X) Multiline Array TVS Diodes in IC and Chip Scale Packaging SurgeArray Suppressors (MLN) Multiline ESD protection array in ceramic chip package
Working Voltage
10,000 3,000
ZA
SP
SM-SGT
MA
ZA
RA
RA
1,000
PA
Nicknamed MLs or MLVs Leadless, Surface Mount Chip Form Combine Surge, ESD, and Filtering Functions Rugged, Robust, Reliable Three distinct versions: ML Series - supports the broadest application range MLE Series - intended for ESD while providing filter functions AUML Series - characterized for the specific transients found in automotive electronic systems
Designed for Low-Voltage DC Applications; 3.5V to 120V Applications can include: ML and MLE Series: Low Voltage, Board Level Products (Hand-Held/Portable devices, Computer/EDP, Instrumentation, Medical Electronics, etc.) AUML and ML Series: Automotive Electronics (Antilock brake systems, Wiper Modules, Airbag control systems, etc.) ML and MLE Series: Telecommunications Products (Cellular/Cordless Phones, Modems, Line Cards, etc.)
The network is a set of four independent multilayer varistors in a single surface mount package (1206). The extended voltage family now includes 5.5, 9, 14, 18 and 18 low capacitance (Product launching standard capacitance now). The inherent capacitance provides filtering capability to eliminate the need for an additional capacitor (450 - 45pF) Reduces board space and assembly placement cost while increasing assembly capacity and system reliability Direct upgrade for AVX(Multiguard) and Epcos(CA06 series)
SurgeArray
The SurgeArray network is a set of four independent Multilayer Varistors in a single surface mount package (1206).
SurgeArray Networks were designed to meet the needs of the Battery Operated, Portable / Handheld, Automotive, and Industrial Markets.
The SurgeArray network helps your customers meet mandatory EMC requirements by suppressing ESD, EFT and other potentially damaging transients either generated or experienced by their systems. The inherent capacitance of Littelfuses Multilayer Varistor Technology provides filtering capability to eliminate the need for an additional capacitors. SurgeArray networks increase component density, thus reducing board space, assembly placement costs, parts count, and system reliability Direct upgrade for AVX(Multiguard) and Epcos (CA06 series).
=
4 0603s = 1 SurgeArray MLV Network
not to scale
SP Series Diode/SCR Arrays The SP72X..A Family of Silicon Bipolar Diode / SCR IC Arrays Designed for Suppression of ESD and Other Transients !
Low Capacitance ( 1-3pF ) Low Leakage ( <1nA ) Suited to Any Supply Voltage 1VDC to 35VDC ( 1 - 20V for the SP724) Clamps to +/- 0.7V of referenced voltage supplies Fast Response for ESD Standard Temperature Range of -40 to +105 deg C Multiple packages
SP720 - 14 lines: 16 pin DIP or SOP SP721 - 6 lines: 8 pin DIP or SOP SP723 - 6 lines: 8 pin DIP or SOP (extended surge) SP724 - 4 lines: 6 pin SOT23
NAFTA 45%
$120 M
The Gap
Tin Plating
Lowest Capacitance (0.050pF) Uses polymer voltage variable material (VVM) instead of electroceramic of MLVs Supplements the on-board TVS protection of ICs and ASICs
Polymer binder
Electrode Width Cu/Ni Electrode Metallic particle Cu/Ni Electrode Semiconductor particle
The Gap
Voltage (V)
Trigger Voltage: The voltage level at which the ESD suppressor turns on; has to be coordinated with existing on-chip protection
Coordination Achieved
TRIGGER
IC is too sensitive
TRIGGER VOLTAGE must be below the sensitivity level of the chip to be protected
Time (ns)
CLAMP
Clamping Voltage: The voltage that the circuit is subjected to from the ESD pulse, after the ESD suppressor turns on
CLAMPING VOLTAGE must be below the withstand voltage of the chip to be protected
< 1pF (0.055 pF); PulseGuard does not interfere with high speed signals.
< 100 pA; PulseGuard pulls virtually no current from battery in portable applications, does not interfere with high input impedance circuits.
Configurability
Minimizes new product lead-time. Custom products can be turned around quickly.
CA10 8 line
Target Applications
Computer
Desktop Laptops/Notebooks Peripherals (Monitor/Display, Printer, Scanner, Plotter) Network Hardware Personal Digital Assistants (PDAs) Flat Panel Displays Digital Set Top Boxes Industrial/Process Controllers Multimedia Interface Hardware Medical and Test Equipment
Electronic
Telecom
Cell Phone Data Ports Secondary side of Network Interface Products
Target Applications
ESD Protection for signal, data and control lines
Cellular Phones PDAs Digital Cameras Printers Set-top boxes Cable Modem DSL Modem Laptop Computers
PDA
Cable Modem
PulseGuard
Polymer VVM Ultra-low capacitance, package flexibility <1.0 55fF measured 3,000 <1.0 ESD only 0 - 24 <1.0 0603, 0805 1206 SOT23 - 2 lines 0805-4 - 4 lines SO8 - 7 lines CA10 - 8 lines
Not available
limits are affected by actual circuit layout by product rating, consult Suppression Products Handbook
Voltage
Time
LOW LEAKAGE CURRENT . Compatible with low-power portable equipment and High-Impedance analog circuits
Magnitude
ESD
Frequency
Filter response of high capacitance suppressors can affect data waveforms Not a problem for low frequency data as the data falls within the band pass Unintended consequence of capacitance is to distort data by filtering the spectrum of the data that falls outside of the band pass
Capacitance Key: V5.5MLA0603 - 660 pF SMD Capacitor - 390 pF V18MLE0603 - 100 pF PGB0010603 - 0.05 pF
Capacitance Key: V5.5MLA0603 - 660 pF SMD Capacitor - 390 pF V18MLE0603 - 100 pF PGB0010603 - 0.05 pF
FAST RESPONSE TIME LOW CLAMPING VOLTAGE HIGH CURRENT HANDLING .... These features give the suppressor the ability to protect
sensitive components against multiple severe ESD events
IC with Internal TVS Structures
Rs
LF ESD
TVS
SMALL SIZE
-- There are no Diodes or MOVs that can provide low capacitance in the 0603 size!!
Examples Computer (networks, peripherals) Flat Panel Displays Personal Digital Assistants (PDAs) Cell phones, pagers Set top boxes (satellite and cable) Medical Equipment Test Instrumentation
USB Controller
VBUS
Outside World
VBUS D+ D-
PTC - 1812L260
PGB0010603 PGB0010603
D+ D-
Signal Ground
Signal Ground
MLV - V5.5MLA0603 Note: ESD suppressor must be installed as close to the connector as possible to minimize overshoot
Shield/Chassis Ground
Signal Ground
USB Port
1812L150 SP0503BAHT
USB Controller
VBUS D+ D-
Outside World
Ground
USB Controller
VBUS 1D+
1D 6 5 4 SP0505BAHT
Outside World
3 2D+ 2D Ground
USB Port 2
1394b Controller
Outside World
Shield/Chassis Ground
Signal Ground
Note: ESD suppressor must be installed as close to the connector as possible to minimize overshoot
PGB0010603
Shield/Chassis Ground
Note: ESD suppressor must be installed as close to the connector as possible to minimize overshoot
Telecom Requires typical telecom protection Incoming E1/T1, xDSL, etc. lines Fuse for UL1950, etal Thyristor for overvoltage 10/100/1,000 Ethernet Requires low capacitance ESD PulseGuard for network lines PGB0010603, PGB002ST23
Antenna - 800 - 1800 MHz - PGB0010603 Keypad - low speed - V9MLA0603 - V18MLN41206 I/O Connector - medium to high speed - V9MLA0603 - V18MLN41206 - PGB0010603 - PGB008CA10
Minimize Distance Between the ESD Event and the ESD Suppressor Maximize Distance Between the ESD Suppressor and the I/C to be Protected Minimize Impedance between the ESD Suppressor and Ground
D1
D2 I/O Line
Due to fast rise time of ESD transient, lengths (trace and lead) become extremely important. They will affect the voltage that is ultimately seen by the IC to be protected.
D3 TVS
Signal Ground
Solution Surface Mount; close to I/O line (D3 is small) Minimize distance to source (D1 is small)
Voltage
Time in nanoseconds
I/O
PG
The length of the PC board trace between PG and I/O pin was approximately 3
Minimize Distance Between the ESD Event and the ESD Suppressor Maximize Distance Between the ESD Suppressor and the I/C to be Protected Minimize Impedance between the ESD Suppressor and Ground
Keep the trace lengths from the I/O line to the Suppressor and from the Suppressor to the Ground plane as short as possible Minimize bends in board traces
D3 TVS
Signal Ground
Solution Surface Mount; close to I/O line (D3 is small) Minimize distance to source (D1 is small)