I/O interfacing

Introduction:
Peripheral devices provide interface between the CPU and slow electromechanical devices Previously, all these devices were taken care of by the CPU using interrupt mechanism or polling techniques, which results in reduced overall efficiency and low processing speed To minimize the slow speed I/O communication overhead, a set of dedicated programmable peripheral devices have been introduced Thus once initiated by the CPU, these devices take care of all the interface activities , and thus makes the CPU free from the interface activities and execute its main task more efficiently.

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Programmable interval Timer 8253

Function and working principle of 8253: The 8253/54 solves one of most common problem in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in system software, the programmer configures the 8253/54 to match his requirements, initializes one of the counters of the 8253/54 with the desired quantity, then upon command the 8253/54 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimum and that multiple delays can be easily be maintained by assignment of priority levels. The 8253/54 includes three identical 16 bit counters that can operate independently. To operate a counter, a 16-bit count is loaded in its register and, on command, it begins to decrement the count until it reaches 0.
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Programmable interval Timer 8253

At the end of the count, it generates a pulse that can be used to interrupt the CPU. The counter can count either in binary or BCD. In addition, a count can be read by the CPU while the counter is decrementing. FEATURES: Three independent 16-bit down counters. Each with maximum count rate of 2.6 MHz . Three counters are identical presettable, down counters and can be programmed for either binary or BCD count. Counter can be programmed in six different modes. Compatible with all Intel and most other microprocessors.
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Programmable interval Timer 8253

FEATURES: 8253 has powerful command called READ BACK command which allows the user to check the count value, programmed mode and current mode and current status of the counter. Architecture and signal descriptions: Three independent 16-bit counters, all these counters may be independently controlled by programming the 3 internal command word registers, thus possible to generate 3 totally independent delays or maintain 3 independent counters simultaneously. It has 8-bit, bidirectional data buffer interfaces internal circuit of 8253 to microprocessor system bus. Data is transmitted or received by the buffer upon the execution of IN (reads data) or OUT(writes data to a peripheral) instruction. Read/write logic controls the direction of the data buffer depending upon whether it is read or write operation.
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I/O Interface

8254 Functional Description

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 Fig. above shows the block diagram of 8253/54. It includes three counters, a data bus buffer, Read/Write control logic, and a control register. Each counter has two input signals CLOCK and GATE and one output signal OUT.
CLK: The clock input is the timing source for each of the internal counters. It is often connected to the PCLK signal from the bus controller. GATE: The gate input controls the operation of the counter in some modes. OUT: A counter output where the wave-form generated by the timer is available.

Programmable interval Timer 8253

Data Bus Buffer : This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54. 2. Loading the count registers. 3. Reading the count values. Advanced Microprocessor

Programmable interval Timer 8253

Read/Write Logic : The Read/Write logic has five signals : RD,WR,CS and the address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are connected to IOR and IOW, respectively. In memory-mapped I/O, these are connected to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word register and counters are selected according to the signals on lines A0 and A1.
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Programmable interval Timer 8253

Read/Write Logic : A low on CS line enables the 8253. No operation will be performed by 8253 till it is enabled. Table below shows the selected operations for various inputs of 8253: CS RD WR A1 A0 selected operation 0 1 0 0 0 write counter 0 0 1 0 0 1 write counter 1 0 1 0 1 0 write counter 2 0 1 0 1 1 write control word 0 0 1 0 0 read counter 0 0 0 1 0 1 read counter 1 0 0 1 1 0 read counter 2 0 0 1 1 1 no operation Advanced Microprocessor 8 0 1 1 x x no operation

Programmable interval Timer 8253

Control Word Register : This register is accessed when lines A0 and A1 are at logic 1 It is used to write a command word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation. Counters : These three functional blocks are identical in operation. Each counter consists of a single, 16 bit, pre-settable, down counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selection of modes stored in the control word register. The counters are fully independent. The programmer can read the contents of any of the three counters without disturbing the actual count in process.

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Programmable interval Timer 8253

Operational Description: The complete functional definition of the 8253/54 is programmed by the system software. Once programmed, the 8253/54 is ready to perform whatever timing tasks it is assigned to accomplish. Programming the 8253/54 : Each counter of the 8253/54 is individually programmed by writing a control word into the control word register (A0 -A1 = 11). The Fig. shows the control word format. Bits SC1 and SC0 select the counter, bits RW1 and RW0 select the read, write or latch command, bits M2,M1 and M0 select the mode of operation and bit BCD decides whether it is a BCD counter or binary counter. The complete functional definition of the 8253/54 is programmed by the system software. Advanced Microprocessor 10 Once programmed, the 8253/54 is ready to perform whatever timing tasks it

Programmable interval Timer 8253 Each counter is individually programmed by writing a control word, followed by the initial count. The control word allows the programmer to select the counter, mode of operation, binary or BCD count and type of operation (read/write).

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Programmable interval Timer 8253 Programming the 8254 Each counter may be programmed with a count of 1 to FFFFH. Each counter has a program control word used to select the way the counter operates. If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte (MSB) starts the counter with the new count.

There are 6 modes of operation for each counter: Mode0, Mode1, Mode2, MOde3, Mode4, Mode5

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Programmable interval Timer 8253 Programming the 8254 Modes of operation Mode 0: interrupt on terminal count. The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts.

Mode 1: One-shot mode.

The G input triggers the counter to output a 0 pulse for count clocks.Counter reloaded if G is pulsed again.

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Programmable interval Timer 8253 Programming the 8254 Modes of operation Mode 2: rate generator or divide by N counter N is loaded as the count value, then after N pulses, the output becomes low only for one clock cycle. The cycle is repeated until reprogrammed or G pin set to 0.

Mode 3: Generates a continuous square-wave with G set to 1. If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

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Programmable interval Timer 8253 Programming the 8254 Modes of operation Mode 4: Software triggered one-shot (G must be 1).

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

Trigger with count of 5

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Programmable interval Timer 8253I/O Interface

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Programmable interval Timer 8253I/O Interface

Read Operations There are three possible methods for reading the counters:
a simple read operation the Counter Latch Command the Read-Back Command Simple read operation : The Counter which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in the process of changing when it is read, giving an undefined result.

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Programmable interval Timer 8253I/O Interface Counter Latch Command: SC0, SC1 bits select one of the three Counters two other bits, D5 and D4, distinguish this command from a Control Word If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.

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Programming
CONTROL WORD FORMAT SC1 SC0 0 0 RL1 1 RL0 1 M2 0 M1 1 M0 0 BCD 0

= 34H(Mode 2)

SC1 0

SC0 0

RL1 1

RL0 1

M2 0

M1 1

M0 1

BCD 0

= 36H(Mode 3)

Control word
SELECT COUNTER BIT DEFINITION
SC0 SC1 OPE RATION

0 0 1 1

0 1 0 1
RL1

Select channel 0 Select channel 1 Select channel 2 Illegeal

OPE RATION

READ\LOAD BIT DEFINITION

RL0

0 0 1 1

0 1 0 1

Latch Counter Read\Load(LSB) Read\Load(MSB) Read\Load LSB first then MSB

MODE
M2 M1 M0 SELECTED MODE MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 0 0 X X 1 1 0 0 1 1 0 0 0 1 0 1 0 1

MODE SELECT BIT DEFINITION

BCD 0 1

OPERATION Hex Count BCD Count

HEX\BCD BIT DEFINITION

Rate Generator
MOV AL,34H OUT 16,AL MOV AL,04H OUT 10,AL MOV AL,00H OUT 10,AL HLT
Move the command word to A register Output it to control register Move 04 to A register Output the value to counter 0 Move 00 to A register Output the value to content 0 Halt the program execution

SQUARE WAVE
MOV AL,36H OUT 16,AL MOV AL,04H OUT 10,AL MOV AL,00H OUT 10,AL HLT
Move the command word to A register
Output it to control register Move 04 to A register Output the value to counter 0 Move 00 to A register Output the value to content 0 Halt the program execution