Lecture 4 Combinational Logic Implementation Technologies

Hai Zhou ECE 303 Advanced Digital Design Spring 2002

ECE C03 Lecture 4 1

Outline
Review of Combinational Logic Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic Multiplexers/Decoders ROM READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

ECE C03 Lecture 4

Programmable Arrays of Logic Gates

Until now, we learned about designing Boolean functions using discrete logic gates We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure Specific functions can be programmed Can use programmable logic arrays (PLA) or programmable array logic (PAL)

ECE C03 Lecture 4

PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

Inputs

Dens e array of AN D gates

Produc t terms

Dens e array of OR gates

Outputs

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Why PALs/PLAs Work

Equations Example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A

Key to Success: Shared Product Terms

Personality Matrix
Produc t Inputs Outputs term A B C F0 F1 F2 F3 0 1 1 0 AB 1 1 BC - 0 1 0 0 0 1 AC 1 - 0 0 1 0 0 BC - 0 0 1 0 1 0 1 0 0 1 A 1 - -

Input Side: 1 = asserted in term 0 = negated in term - = does not participate Output Side: 1 = term connected to output Reuse 0 = no connection to output of terms

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Example of PALs and PLAs

All possible connections are available before programming

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Example of PALs and PLAs (Contd)

Unwanted connections are "blown"

Note: some array structures work by making connections rather than breaking them
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Alternative Representations
Short-hand notation so we don't have to draw all the wires!

Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

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Design Example
Multiple functions of A, B, C
F1 = A B C F2 = A + B + C
ABC A B C A B

F3 = A B C
F4 = A + B + C F5 = A xor B xor C

C ABC ABC

F6 = A xnor B xnor C

ABC ABC ABC ABC ABC

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F1

F2

F3

F4 F5

F6

Differences Between PALs and PLAs

PAL concept implemented by Monolithic Memories constrained topology of the OR Array

A given column of the OR array has access to only a subset of the possible product terms

PLA concept generalized topologies in AND and OR planes

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Design Example: BCD-to-Gray Code Converter Truth Table K-maps

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X
AB CD 00 01 11 C 10 0 1 B K-map for W A 00 0 0 1 1 01 1 1 1 1 B K-map for Y 11 X X X X 10 0 0 D 11 X C 10 X 10 1 0 B K-map for Z X X 11 0 1 X X C X X 00 0 0 0 01 0 1 1 11 X X X A 10 1 1 D X C 10 0 0 B K-map for X A 00 0 1 01 0 0 11 X X 10 1 0 D X X 11 0 0 X X AB CD 00 01 00 0 0 01 1 1 11 X X A 10 0 0 D

AB CD 00 01

AB CD 00 01

Minimized Functions: W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D'

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Programmed PAL

0 0 0

0
0 ABCD

ECE C03 Lecture 4 product terms per each OR gate4

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Non-Gate Logic
So far we have seen: AND-OR-Invert PAL/PLA Generalized Building Blocks Beyond Simple Gates

Kinds of "Non-gate logic": switching circuits built from CMOS transmission gates multiplexer/selecter functions decoders tri-state and open collector gates read-only memories

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Steering Logic: Switches

Voltage Controlled Switches
Gate Oxide Source Silicon Bulk Drain Channel Region

n-type Si p-type Si

"n-Channel MOS" Metal Gate, Oxide, Silicon Sandwich Diffusion regions: negatively charged ions driven into Si surface Si Bulk: positively charged ions By "pulling" electrons to the surface, a conducting channel is formed
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Switching or Steering Logic

Voltage Controlled Switches

Gate Source Drain nMOS Transistor Gate Source

Logic 0 on gate, Source and Drain connected Logic 1 on gate, Source and Drain connected

Drain pMOS Transistor

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Logic Gates with Steering Logic

Logic Gates from Switches
+5V +5V A B +5V A B

AB A+B

Inverter

NAND Gate

NOR Gate

Pull-up network constructed from pMOS transistors Pull-down network constructed from nMOS transistors
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Inverter with Steering Logic

Inverter Operation
+5V +5V

"1"

"0"

"0"

"1"

Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND
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Input is 0 Pull-up conducts Pull-down does not conduct Output connected to VDD
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NAND Gate with Steering Logic

NAND Gate Operation
"1" +5V "1" +5V "0" "1"

"0"

"1"

A = 1, B = 1 Pull-up network does not conduct Pull-down network conducts Output node connected to GND
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A = 0, B = 1 Pull-up network has path to VDD Pull-down network path broken Output node connected to VDD
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NOR Gate with Steering Logic

NOR Gate Operation
"0" +5V "0" +5V "1" "0"

"1"

"0"

A = 0, B = 0 Pull-up network conducts Pull-down network broken Output node at VDD

A = 1, B = 0 Pull-up network broken Pull-down network conducts Output node at GND

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CMOS Transmission Gate

nMOS transistors good at passing 0's but bad at passing 1's pMOS transistors good at passing 1's but bad at passing 0's perfect "transmission" gate places these in parallel:
Control Control Control

In

Out

In

Out

In

Out

Control

Control

Control

Switches

Transistors
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Transmission or "Butterfly" Gate

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Selection/Demultiplexing

Selector: Choose I0 if S = 0 Choose I1 if S = 1

S
I 1

Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1

Z0
I S S Z1 S

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Use of Multiplexers or Demultiplexers

A Y Demultiplexers Multiplexers

Demultiplexers

Multiplexers

So far, we've only seen point-to-point connections among gates Mux/Demux used to implement multiple source/multiple destination interconnect ECE C03 Lecture 4 22

Well-formed Switching Logic

Problem with the Demux implementation: multiple outputs, but only one connected to the input!
S Z0 S "0" I S S Z1 S

"0"
S

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"
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Use of Multiplexers/Selectors
Multi-point connections

A0

A1

B0

B1

Multiple input sources

Sb

Sa

MUX

MUX

Sum

Ss

DEMUX

Multiple output destinations

S0

S1

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General Concept of Using Multiplexers

2 data inputs, n control inputs, 1 output n used to connect 2 points to a single point control signal pattern form binary index of input connected to output Z = A' I 0 + A I 1 n

A 0 1

Z I0 I1

Functional form Logical form

I1 0 0 0 0 1 1 1 1

I0 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

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Two alternative forms for a 2:1 Mux Truth Table 25

I0 I1

Use of Multiplexers/Selectors 2:1

mux Z

Z = A' I 0 + A I 1

A I0 I1 I2 I3

4:1 mux

Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

A I0 I1 I2 I3 I4 I5 I6 I7

8:1 mux

Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 n -1 2 In general, Z = S m I k=0 k k in minterm shorthand form for a 2 n :1 Mux
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Alternative Implementation
A B

I0

I1

I2

I3

Gate Level Implementation of 4:1 Mux thirty six transistors

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Transmission Gate Implementation of 4:1 Mux twenty transistors

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Large multiplexers can be implemented by cascaded smaller ones

I0 I1 I2 I3 I4 I5 I6 I7 0 4:1 1 mux 2 3S S
1

Design of Large Multiplexers

8:1 mux 0 2:1 mux 1 S Z

Control signals B and C simultaneously choose one of I0-I3 and I4-I7

Control signal A chooses which of the upper or lower MUX's output to gate to Z
I0 0

0 4:1 1 mux 2 3S S
1

I1

1 S
C

I2 I3

0 1 S C

0
1 Z S1

Alternative 8:1 Mux Implementation

I4 I5 0

2 3 S0

1 S C A B

I6 I7

0 1 S

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C

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Multiplexers/Selectors as General Purpose Blocks n-1

:1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux Example: F(A,B,C) = m0 + m2 + m6 + m7 = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1)
1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7

8:1 MUX

S2 S1 S0 A B C

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

C
C 0 1

C C 0 1

0 1 2 3

4:1 MUX
S1
A

S0
B

"Lookup Table"
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Generalization of Multiplexer/Selector Logic F I I I

1 2 n

n-1 Mux control variables single Mux data variable

0 1

0 0 0

0 1 In

1 0 In

1 1 1

Four possible configurations of the truth table rows Can be expressed as a function of In, 0, 1

Example: G(A,B,C,D) can be implemented by an 8:1 MUX: K-map Choose A,B,C as control variables
1 D 0 1 D D D D 0 1 2 3 4 5 6 7

8:1 mux

Multiplexer Implementation
TTL package efficient May be gate inefficient
ECE C03 Lecture 4

S2 A

S1 B

S0 C 30

Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
n

outputs

control inputs (called select S) represent Binary index of output to which the input is connected data input usually called "enable" (G) 1:2 Decoder: O0 = G S; O1 = G S 2:4 Decoder: O0 = G S0 S1 O1 = G S0 S1 O2 = G S0 S1 O3 = G S0 S1

3:8 Decoder: O0 = G S0 S1 S2
O1 = G S0 S1 S2 O2 = G S0 S1 S2 O3 = G S0 S1 S2 O4 = G S0 S1 S2 O5 = G S0 S1 S2 O6 = G S0 S1 S2
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O7 = G S0 S1 S2

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Alternative Implementations
G Select Output1 Output0

/G Select

Output0 Output1

1:2 Decoder, Active High Enable

1:2 Decoder, Active Low Enable

G Output0 Output1 Output2 Output3

/G Output0 Output1 Output2 Output3

Select0

Select1

Select0

Select1

2:4 Decoder, Active High Enable

2:4 Decoder, Active Low Enable

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ECE C03 Lecture 4

Switch Level Implementations

Select

Select G Select Select Output 1 Select Output 0

G Select Select "0" Select Select

Output

Output Select

Naive, Incorrect Implementation

Select

All outputs not driven at all times

"0" Select

Correct 1:2 Decoder Implementation

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Switch Implementation of 2:4 Decoder

Select 0 Select 1 G Output 0

"0" "0"

Operation of 2:4 Decoder S0 = 0, S1 = 0

Output 1

one straight thru path three diagonal paths

"0" "0"

Output

"0" "0"

Output

"0"
"0"

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Decoder as a Logic Building Block

0 1 2 3 4 5 6 7
ABC ABC ABC ABC ABC ABC ABC ABC

Enb

3:8 dec

Decoder Generates Appropriate Minterm based on Control Signals

S2 A

S1 B

S0 C

Example Function: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D')

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Decoder as a Logic Building Block

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD

F1

Enb

4:16 dec

F2

S3 S2 S1 S0 A B C D

F3

If active low enable, then use NAND gates!

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Read-Only Memories
ROM: Two dimensional array of 1's and 0's

Row is called a "word"; index is called an "address"

Width of row is called bit-width or wordsize Address is input, selected word is output
+5V +5V +5V +5V

n 2 -1 i j 0 Bit Lines Word Line 0011

Dec

Word Line 1010

n-1 Address

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Implementing Logic with ROMs

F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C'
Address A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 Word Contents

ROM 8 w ords by 4 bits

A B C address

F0

F1

F2

F3
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outputs

ROMs vs PLAs
Not unlike a PLA structure with a fully decoded AND array!
Memory array Decoder 2n words by m bits 2n word lines

n address lines

m output lines

ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions
ECE C03 on Lecture 4 planes PAL problem: constrained fan-ins OR 39

Summary
Review of Combinational Logic Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic Multiplexers/Decoders ROM READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

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