Interfacing with Advanced Devices

By K. SAI KRISHNA Assistant Professor 1

INTRO TO I/O INTERFACE

I/O instructions are IN, INS, OUT, and OUTS

Also isolated (direct I/O or mapped I/O) and memory-mapped I/O, the basic input and output interfaces, and handshaking.
Knowledge of these topics makes it easier to understand the connection and operation of the programmable interface components and I/O techniques.
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Interfacing Configurations
2 Types
1. Memory mapped I/O 2. I/O mapped I/O (Isolated I/O)

Interfacing Configurations
Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH), isolated from the memory address space. Memory mapped I/O: uses memory reference instructions (e.g. MOV). So address space is shared between memory and I/O (used by only one of them). Both techniques can be used with Intel processors. But most Intel-based systems use isolated I/O.

Memory: MOV

a. Isolated I/O Using dedicated I/O instructions e.g. IN, OUT

64 K I/O bytes

b. Memory-mapped I/O Using ordinary memory transfer instructions e.g. MOV

I/O: IN

MOV Range of memory addresses assigned for I/O transfers Memory

Memory Mapped I/O

Memory-Mapped I/O
Memory-mapped I/O does not use the IN or OUT instructions.

It uses any instruction that transfers data between the microprocessor and memory.
treated as a memory location in memory map

Advantage is any memory transfer instruction can access the I/O device.
Disadvantage is a portion of memory system is used as the I/O map.
reduces memory available to applications

Isolated I/O
I/O devices are treated separately from memory Address 0000 to 00FF is referred to page 0.

Special instructions exist for this address range Byte wide ports
Word wide ports
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Isolated I/O
The most common I/O transfer technique used in the Intel-based system is isolated I/O.

Isolated describes how I/O locations are isolated from memory in a separate I/O address space Addresses for isolated I/O devices, called ports, are separate from memory.
Because the ports are separate, the user can expand the memory to its full size without using any of memory space for I/O devices.
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Memory interface
Memory is a device to store data.

To interfacing with memories, there must be:

address bus, data bus and control signals (chip

enable, output enable etc)

To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory

Block diagram of a memory interface

Content Address FFFF

Data

0000

Control signals Include enable (chip select) , read/write

Memory Banking

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INTERFACING WITH MEMORIES

The figure 1 shows a general block diagram of an 8086 memory array. In this, the 16-bit word memory is partitioned into high and low 8-bit banks on the upper halves of the data bus selected by BHE, and AO.
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a) ROM and EPROM ROMS and EPROMs are the simplest memory chips to interface to the 8086.

Since ROMs and EPROMs are read-only devices, A0 and BHE are not required to be part of the chip enable/select decoding. The 8086 address lines must be connected to the ROM/EPROM chip chips starting with A1 and higher to all the address lines of the ROM/EPROM chips. The 8086 unused address lines can be used as chip enable/select decoding. To interface the ROMs/RAMs directly to the 8086-multiplexed bus, they must have output enable signals. The figure 2 shows the 8086 interfaced to two 2716s. Byte accesses are obtained by reading the full 16-bit word onto the bus with the 8086 discarding the unwanted byte and accepting the desired 14 byte.

Interrupts
Definition: The meaning of interrupts is to break the
sequence of operation. While the CPU is executing a program, on interrupt breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After

executing ISR , the control is transferred back again to the

main program. Interrupt processing is an alternative to polling.

Need for Interrupt: Interrupts are particularly useful when

interfacing I/O devices that provide or require data at relatively low data transfer rate.
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Different Types of Interrupts

INTERRUPTS
HARDWARE INTERRUPTS INTERNAL SOFTWARE INTERRUPTS

EXTERNAL

SYSTEM

USER-DEFINED

MASKABLE

NON-MASKABLE

DOS INTERRUPTS

BIOS INTERRUPTS

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Computer Interrupt
2 General Types of Interrupts:

External - generated outside CPU by other hardware Internal - generated within CPU as a result of instruction or operation
- x86 internals: int, into, divide error, and single step - trap generally means any processor generated interrupt; in x86, usually means the single step interrupt
x86 Terminology for Interrupts:

1) Hardware Interrupt External, uses INTR and NMI control bus lines 2) Software Interrupt Internal, from int or into 3) Processor Interrupt traps, exceptions

Classification 8086 INTERRUPTS

256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS
1. TYPE 0 TO TYPE 4 INTERRUPTSTHESE ARE USED FOR FIXED OPERATIONS AND HENCE ARE CALLED DEDICATED INTERRUPTS TYPE 5 TO TYPE 31 INTERRUPTS NOT USED BY 8086,RESERVED FOR HIGHER PROCESSORS LIKE 80286 ,80386 ETC TYPE 32 TO 255 INTERRUPTS AVAILABLE FOR USER,CALLED USER DEFINED INTERRUPTS THESE CAN BE H/W INTERRUPTS AND ACTIVATED THROUGH INTR LINE OR CAN BE S/W INTERRUPTS

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3.

TYPE 0 DIVIDE ERROR INTERRUPT

QUOTIENT IS LARGE CANT BE FIT IN AL/AX OR DIVIDE BY ZERO

TYPE 1 SINGLE STEP INTERRUPT

USED FOR EXECUTING THE PROGRAM IN SINGLE STEP MODE BY SETTING TRAP FLAG TO SET TRAP FLAG PUSHF MOV BP,SP OR [BP+0],0100H;SET BIT8 POPF

TYPE 2 NON MASKABLE INTERRUPT

THIS INTERRUPT IS USED FOR EXECUTING ISR OF NMI PIN (POSITIVE EGDE SIGNAL). NMI CANT BE MASKED BY S/W

TYPE 3 BREAK POINT INTERRUPT

USED FOR PROVIDING BREAK POINTS IN THE PROGRAM

TYPE 4 OVER FLOW INTERRUPT

USED TO HANDLE ANY OVERFLOW ERROR AFTER SIGNED ARITHMETIC

PRIORITY OF INTERRUPTS
INTERRUPT TYPE
INT0,INT3-INT 255,INTO

PRIORITY
HIGHEST

NMI(INT2)

INTR

SINGLE STEP

LOWEST

Interrupt Vector Table IVT (in memory)

x86 has 256 interrupts, specified by Type Number or Vector 1 byte of data must accompany each interrupt; specifies Type Vector is a pointer (address) into Interrupt Vector Table, IVT
IVT is stored in memory from 0000:0000 to 0000:03ffh

IVT contains 256 far pointer values (addresses)

Far pointer is CS:IP values

Each far pointer is address of Interrupt Service Routine, ISR

Also referred to as Interrupt Handler

IVT Format
0000:0000 0000:0001

Offset Interrupt 0 Segment Offset Interrupt 1

IP LSB IP MSB CS LSB CS MSB

0000:0002
0000:0003 0000:0004 0000:0005 0000:0006 0000:0007

Segment
Given a Vector, where is the ISR address stored in memory ?

Offset Type 4
0000:03fc 0000:03fd 0000:03fe 0000:03ff

Offset Interrupt 255

Example:

int 36h

Segment

Offset = (544) = 216 = 00d8h

Structure of Interrupt Vector Table 8086/88

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Interrupt Service Routine (ISR)

Similar to a subroutine Attends to the request of an interrupting source
Clears the interrupt flag Should save register contents that may be affected by the code in the ISR Must be terminated with the instruction RETFIE

When an interrupt occurs, the MPU:

Completes the instruction being executed Disables global interrupt enable Places the return address on the stack

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Interrupt Service Routine (ISR)

High-priority interrupts
The contents of W, STATUS, and BSR registers are automatically saved into respective shadow registers.

Low-priority interrupts
These registers must be saved as a part of the ISR
If they are affected

RETFIE [s] RETFIE FAST

;Return from interrupt ;FAST equivalent to s = 1

If s =1: MPU also retrieves the contents of W, BSR, and STATUS registers

DOS & BIOS Introduction

BIOS functions (Basic Input/ Output System) INT10 Video services INT13 Disk Services INT16 Keyboard functions INT17 Parallel printer functions

Reserved INTs

DOS functions INT21 (Disk Operating System)

keyboard display printer disk date/time memory management program control

DOS Functions-Using the Keyboard

DOS INT 21, function 01H: Wait for Keyboard Input
Specification: waits for the user to press a key on the keyboard and returns the ASCII code.
Ex: MOV ah, 01H; Request keyboard input INT 21h

Input: AH = 01 (function code)

Output: AL = ASCII code of the pressed key. The character is echoed to the video display

Constrain: doesnt return the control to the main program until a key is
pressed. If the key correspond to an extended ASCII code, AL returns 00. The next INT 21, function 01 returns in AL the extended ASCII code.

DOS INT 21, function 08H: Console Input without Echo

Specification: similar to function 01 but no echo on video display.
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Controlling the Video Display

DOS INT 21, function 02H: Display Output
Specification: writes a single character to the display screen, at the current cursor position.
Ex: MOV AH, 02h;request character display MOV DL, S INT 21h

Input: AH = 02 (function code), DL = ASCII character to be sent to display.

Control characters perform their specific action (0DH = Carriage Return, 0AH = Line Feed, 08H = Backspace, etc.).

DOS INT 21, function 09H: Display A CHARACTER String

Specification: Send to display a string in the current data segment. The string ends with $ character (not displayed).

Input: AH = 09 (function code), DX = The offset of the first character in the

string.
Ex: String DB Enter your name: $ MOV AH, 09h; request display LEA DX, String; load address INT 21h

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BIOS Functions: Using the Keyboard

BIOS INT 16, function 00H: Read keyboard Input
Specification: similar to INT21 function 01 but if the pressed key correspond to an extended ASCII code, AL returns 00 and AH returns the extended ASCII code. No echo to display.

BIOS INT 16, function 01H: Read keyboard status

Specification: doesnt wait. If the keyboard buffer is empty, ZF is set to 1. If not, returns the first ASCII code from buffer in the same way like function 00, and clear ZF.

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Using the Keyboard(Contd)

BIOS INT 16, function 02H: Return Shift Flag Status
Specification: waits for the user to press a key on the keyboard and returns the ASCII code. Input: AH = 02 (function code) Output: AL = Status of the special function keys: B7=Insert, B6=Caps Lock, B5=Num Lock, B4=Scroll Lock (active bit=1 => function active) B3=Alt, B2=Ctrl, B1=Left Shift, B0=Right Shift (active bit=1 => button

pressed )

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Controlling the Video Display(Contd)

BIOS INT 10, function 00H: Set Video Mode Specification: set video mode of the display (ex: mode 1 = 25 linesX40 characters, mode 3 = 25 linesX80 characters).

Input: AH = 00 (function code), AL = The desired video mode .

BIOS INT 10, function 0FH: Read Current Video Mode Specification: returns video mode of the display.
Input: AH = 0F (function code) Output: AL = The current video mode.

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Controlling the Video Display(Contd)

BIOS INT 10, function 02H: Set Cursor Position
Specification: moves the cursor to specified position (in text mode).
Input: AH = 02 (function code), DH = the row (0-24), DL column (0-79), BH = page (0)

BIOS INT 10, function 03H: Read the Current Cursor Position Input: AH = 02 (function code), BH = page (0) Output: DH = the row (0-24), DL column (0-79)

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Controlling the Video Display(Contd)

BIOS INT 10, function 0AH: Write Character to Screen
Specification: write multiple times a character to screen at current cursor position.

Input: AH = 0A (function code), AL = ASCII code, BH = page number, CX =

repeat value.

BIOS INT 10, function 09H: Write Character/Attribute to

Screen
Specification: write multiple times a character to screen at current cursor position. Specify the video attribute of the character: B7 = blink, (B6 = red, B5 = green, B4 = blue)=background, B3 = intensity, (B2 = red, B1 = green, B0 = blue)=foreground Input: AH = 09 (function code), AL = ASCII code, BH = page number,
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BL = characters attribute, CX = repeat value.

Controlling the Video Display(Contd)

BIOS INT 10, function 08H: Read Character/Attribute from
Screen
Input: AH = 08 (function code), BH = display page (0)

Output: AL = The Character code at the current cursor position, AH = the

attribute byte.

BIOS INT 10, function 06H: Scroll Current Page Up

Input: AH = 06 (function code)
AL = Number of rows to scroll up (0 for entire region) BH = attribute for scrolled region

CH = Row number at top of region

CL = Column number at left of the region DH = Row number at bottom of region DL = Column number at right of the region
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Examples: in the textbook!

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8259 Features
8259 is Programmable Interrupt Controller (PIC) It is a tool for managing the interrupt requests.
8259 is a very flexible peripheral controller chip:
PIC can deal with up to 64 interrupt inputs interrupts can be masked individually. various priority schemes can also programmed.

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8259 Pin Diagram

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Pin Details

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Interfacing 8259

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Block Diagram

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Working of 8259
1. One or more of the INTERRUPT REQUEST lines (IR0IR7) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA* pulse.

4. Upon receiving an INTA* from the CPU group, the highest priority ISR bit is set and the corresponding IRR bit is reset.
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Working of 8259
5. Then 8086 will send one more INTA pulse to 8259.
On this second interrupt acknowledge cycle, 8259 will send an interrupt vector byte of data to the CPU, which is a pointer of the interrupt to be processed. This completes the interrupt cycle.

5.

6. The ISR bit is reset at the end of the 3rd INTA pulse.

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Work flow inside 8259

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8259 Command Words

There are 2 Command Words in 8259. 1. Initialization Command Words (ICWs): Before normal operation can begin, each 82C59A in the system must be brought to a starting point using these command words.
There are 4 ICWs in 8259.

2. Operation Command Words (OCWs): These are the command words which command the 82C59A to operate in various interrupt modes.
There are 3 OCWs in 8259
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ICW1 Format

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ICW2 Format

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 This word is read only when there is more than one 8259 in the system and cascading is used, in which case SNGL = 0 in ICW1.

ICW3 Format

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ICW4 Format

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Operation Command Words (OCWs)

After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready to accept interrupt requests at its input lines. However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words (OCWs).

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OCW1 Format

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OCW2 Format

R, SL, EOI: These three bits control the Rotate and End of Interrupt modes and combinations of the two. L2, L1, L0: These bits determine the interrupt level acted upon 51 when the SL bit is active.

OCW3 Format

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8259A initialization sequence

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8259 Working Modes

There are 4 different modes for 8259.

1. Fully nested mode. 2. Rotating priority mode. 3. Special mask mode. 4. Polled mode.

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Cascaded Mode

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Fully nested mode

This mode is entered after initialization unless another mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus.

Additionally, a bit of the Interrupt Service register (ISO-7) is set.

This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine If AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. 56

Rotating priority mode

In some applications there are interrupting devices of equal priority. a number of

In this mode, a device after being serviced, receives the lowest priority.

So a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once .

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Special mask mode

Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion.

That is where the Special Mask Mode comes in.

In the special Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading 58 the mask register.

Polled mode
In Polled mode the INT output functions as it normally does.

The microprocessor should ignore this output.

This can be accomplished either by not connecting the INT output or by masking interrupts within the microprocessor, thereby disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P = 1 in 59 OCW3.

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Direct memory access

Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the CPU. DMA is for high-speed data transfer from/to mass storage peripherals, e.g. hard disk drive, magnetic tape, CD-ROM, and sometimes video controllers. The basic idea of DMA is to transfer blocks of data directly between memory and peripherals. The data dont go through the microprocessor but the data bus is occupied.
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Basic process of DMA Minimum Mode

The HOLD and HLDA pins are used to receive and acknowledge the hold request respectively. Normally the CPU has full control of the system bus.

In a DMA operation, the peripheral takes over bus control temporarily.

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Basic process of DMA Maximum Mode

The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals. Sequence of events of a typical DMA process:
1. Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority)

2. 8086 completes its current bus cycle and enters into a HOLD state.
3. 8086 grants the right of bus control by asserting a grant signal via the same pin as the request signal. 4. DMA operation starts. 5. Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control. 63

DMA controller
A DMA controller interfaces with several peripherals that may request DMA.

The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer. DMA controller commonly used with 8086 is the 8257/8237 programmable device.
The 8257/8237 is a 4-channel device. Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory. 64

8237 - DMA Controller

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8237 Registers
1. Current address register 2. Current word register 3. Command register 4. Mode register

5. Request register
6. Mask register 7. Status register 8. Temporary register
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8237 Registers
1.Current address register One 16-bit register for each channel Holds address for the current DMA transfer 2.Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from zero to FFFFH 3.Command register Used to program 8257

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8237 Registers
4.Mode register Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel 5.Request register For software-initiated DMA 6.Mask register Used to disable a specific channel

7.Status register
8.Temporary register Used for memory-to-memory transfers
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Types of data transfer

8237 supports four types of data transfer
1. Single cycle transfer Only single transfer takes place Useful for slow devices 2. Block transfer mode Transfers data until TC is generated or external EOP signal is received 3. Demand transfer mode Similar to the block transfer mode In addition to TC and EOP, transfer can be terminated by deactivating DREQ signal 4. Cascade mode Useful to expand the number channels beyond four
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Command Register

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Mode Register

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Request Register

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Mask Register

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Status Register

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Thank you

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