Description, vocabulaire
Un ADC a pour rle de fournir un nombre entier
Une tension possde par dfinition une infinit de valeurs possibles (grandeur analogique) le nombre entier fourni, est forcment limit en quantit de valeurs.
Description, vocabulaire
Le quantum (ou rsolution) d'un ADC est l'incrment
ADC 1024 points ADC 10 bits ADC dont l'tendue de mesure est 5V et le quantum vaut 4,883mV
chantillonneur-Bloqueur
La tension e(t) volue de manire exponentielle cause du condensateur et de la rsistance quivalente du circuit. Il est donc ncessaire, suivant la valeur de cette rsistance, de tenir l'chantillonneur ferm un certain temps, tacq.
Temps
de conversion, tconv : Ds lors que l'chantillonneur est ouvert, la tension e(t) reste constante, et la conversion peut commencer.
via
un
registre
de
Suite
simplement le temps ncessaire une conversion totale, depuis la demande de conversion, jusqu' l'criture du rsultat dans le registre associ.
Priode d'chantillonnage, Te : C'est l'intervalle de
2 voies internes: connectes au capteur de temprature intgr dans le STM32F4 et une rfrence interne (VREFINT = 1.2V)
Fonctionnalits ADC(2/3)
2 groupes de conversion :
Fonctionnalits ADC(3/3)
Alignement droite et gauche des donnes converties
Un Watchdog analogique selon deux seuils high et low Gnration dinterruption :
La fin de la conversion La fin dune conversion injecte Activation du Watchdog analogique
ADCCLK
PCLK2
ADC_IN0 ADC_IN1
DMA Request
Injected data registers (4x12bits) Regular data register (12bits)
End of conversion End of injected conversion
Address/data bus
. . .
ADC_IN15
Injected Channels
Up to 16
Regular Channels
Analog Watchdog
TIM1_TRGO TIM1_CC4 TIM1_TRGO TIM2_CC1 TIM3_CC4 TIM4_TRGO Ext_IT_15 JEXTSEL[2:0] bits Start Trigger (injected group) JEXTRIG bit
AWD
EOC
JEOC
Flags
AWDIE
TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 Ext_IT_11 EXTSEL[2:0] bits EXTRIG bit Start Trigger (regular group)
EOCIE
JEOCIE
Programmation (Mise 1 du START bit : ADON du ADC_CR2) Un trigger externe gnr par :
Timer1 CC1 Timer1 CC2 Timer1 CC3 Timer2 CC2 Timer3 TRGO Timer4 CC4 EXTI Line11
NB: Ltude des voies injectes de lADC (Injected channel) ne fait pas partie de ce cours
ADC
1.5 cycles 7.5 cycles
1.5 cycles 7.5 cycles 13.5 cycles 28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles 239.5 cycles
PCLK2
ADC Prescalers: 2, 4, 6 and 8
13.5 cycles
ADCCLK
28.5 cycles
41.5 cycles
55.5 cycles 71.5 cycles 239.5 cycles
SMPx[2:0]
Squenceur
Squenceur : Permet de dfinir Ordre de conversion des entres La priode dchantillonnage de chaque entre Possibilit de sur-chantillonnage dune ou plusieurs entres
Exemple: - Conversion des voies: 1, 2, 8, 4, 7, 3 et 11
1.5 cycles
13.5 cycles
7.5 cycles
7.5 cycles
71.5 cycles
28.5 cycles
1.5 cycles
Start
Start
CHx
CHx
Single channel continuous conversion mode
. . .
CHn
CHn
Stop
conversion et rcupre le rsultat dans le registre associ, soit en scrutant le drapeau EOC, soit en attendant l'entre en interruption. Mode auto conversion : l'utilisateur lance une conversion, et ds que l'ADC finit sa conversion, il en lance une autre, ventuellement sur un autre canal, et ce de manire cyclique.
Les rsultats sont donc lire rgulirement, sinon ils sont perdus. Les rsultats peuvent tre stocks dans une table de registres internes au priphrique, ou directement en utilisant le contrleur DMA (Direct Memory Access).
. . .
ADC_IN15 Temp Sensor VREFINT
Analog Watchdog
AWD
Status Register
Bits 31:5 Reserved, must be cleared Bit 4 : STRT: Regular channel Start flag
This
bit is set by hardware when regular channel conversion starts. It is cleared by software. 0: No regular channel conversion started 1: Regular channel conversion has started
bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR. 0: Conversion is not complete 1: Conversion complete
bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. 0: No Analog watchdog event occurred 1: Analog watchdog event occurred
20
Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count Bit 11 DISCEN: Discontinuous mode on regular channels Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
Bits 31:24 Reserved, must be kept cleared. Bit 23 TSVREFE: Temperature sensor and VREFINT enable
22
ADC_SMPR2
These bits are written by software to define the high threshold for the analog watchdog.
These bits are written by software to define the low threshold for the analog watchdog.
24
ADC_SQR2
ADC_SQR3
Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. SQx[4:0]: xth conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the xth in the conversion sequence.
25
In ADC1: In dual mode, these bits contain the regular data of ADC2. In ADC2 and ADC3: these bits are not used. These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned
26
ADCX_READ
ADCx_Init
Prototype void ADCx_Init();
Description
This routines configures ADC module. The internal ADC module is set to: single channel conversion 12-bit resolution for ST devices. unsigned integer data format VRef+ : AVdd, VRef- : AVss
Example
ADCx_Init_Advanced
Prototype void ADCx_Init_Advanced(unsigned short _external_reference, unsigned short _adc_resolution);
Description Parameters
This routine configures the internal ADC module to work with user defined settings.
Example
ADC_Set_Input_Channel
Prototype Description Parameters void ADC_Set_Input_Channel(unsigned input_mask); The function sets appropriate ADC channel as an analog input. Input_mask : represents the channel which will be set as an analog input: Can be : _ADC_CHANNEL_x, where x :[0..15] Or _ADC_CHANNEL_ALL
Example
ADC_Set_Input_Channel(_ADC_CHANNEL_0 | _ADC_CHANNEL_1);
ADCx_Get_Sample
Prototype Description
unsigned ADCx_Get_Sample(unsigned channel); The function enables ADC module and reads the specified analog channel input.
channel: represents the channel which will be set as an analog input: Can be : _ADC_CHANNEL_x, where x :[0..15] Or _ADC_CHANNEL_ALL 10-bit unsigned value from the specified channel. unsigned adc_value; ... ADC_Set_Input_Channel(_ADC_CHANNEL_10); // Set ADC channel 10 as an analog input ADC1_Init(); // Initialize ADC module adc_value = ADC1_Get_Sample(10); // read analog value from ADC module Channel 10
Parameters
Returns Example
ADCx_Read
Prototype Description
unsigned ADCx_Read(unsigned channel, unsigned short _external_reference); The function sets appropriate ADC channel as an analog input, enables ADC module, initializes ADC module and reads the specified analog channel input.
channel: represents the channel which will be set as an analog input: Can be : _ADC_CHANNEL_x, where x :[0..15] Or _ADC_CHANNEL_ALL
Parameters
Returns Example
10-bit unsigned value from the specified channel. unsigned adc_value; adc_value = ADC1_Read(10); // read analog value from ADC1 module channel 10
Exemple 10
Relier lentre PA3 une tension analogique, selon la valeur lue une des diodes 3,4,5 ou 6 est allume
Spcifications
1) plateforme: STM32 F4 discovery 2) CPU: STM32F407VG 8Mhz 3) entres: PA3 entre analogique; mappe sur channel3 ( _ADC_CHANNEL_3) 4) sorties: PD12, PD13, PD14 et PD15 - PD12 vers LD4 (LED Verte) - PD13 vers LD3 (LED Orange) - PD14 vers LD5 (LED Rouge) - PD15 vers LD6 (LED Bleue)
Masse 5V
Code
Partie 1 :Configuration
Code
Partie 2 :