Oscillators
We have looked at simple oscillator designs using an inverter, and had a brief look at crystal oscillators. In this presentation, we introduce the 555 timer; a versatile device that is easier to calculate, design and configure in a variety of ways.
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A Versatile Device
The 555 Timer is one of the best known ICs.
The 555 is part of every experimenter's tool kit Capable of creating a wide variety of circuits, including: Oscillators with adjustable frequency and Duty Cycle Monostable Multivibrators Analog to digital Converters Frequency Meters Many other applications. The clock on the Vulcan Board is generated by a 555 timer.
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There are many other configurations and applications for this device.
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555 Layout
Ground Trigger Output Reset
1 2 3 4
8 7 6 5
Also available: 556 (two-555s in one DIP package) 555 in a metal can configuration
Vcc Ground 1 Trigger 2 Output 3
Discharge
6 Threshold 4
Reset
5 Control
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Astable Multivibrator
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Oscillator Configuration
Externally, the 555 requires an RC circuit to create the time delays required for the time high and the time low. Standard configuration requires
common capacitor a resistor for the charge cycle a resistor for the discharge cycle
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General Configuration
Basic connections:
Ground Vcc Note: some 555 timers may function at voltages other than 5 volts. Reset (active low) Output
Ground Trigger Output Reset
1 2 3 4
8 7 6 5
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General Configuration
Specialized connections:
Trigger monitors low voltage Threshold monitors high voltage Discharge path to ground, to discharge the capacitor Control specialized input filtering special applications
Ground Trigger Output Reset
1 2 3 4
8 7 6 5
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Astable Configuration #1
(Standard Configuration)
Vcc
Vcc
Vcc Ra Discharge
1 2 3 4
8 7 6 5
Control
Rb
Threshold Trigger C
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Astable
Calculated Values
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Astable Configuration #1
(Standard Configuration)
t1 Ra Rb DC t1 t2 Ra 2Rb
Minimum duty cycle > 50%
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Calculations: Astable
Time High, Time Low Set
TL 0.693 R B C TH 0.693(R A R B )C
TH TL
Notes: The value 0.693 is a factor associated with the charge/discharge cycle of the 555 timer.
Sample Calculation
Time High, Time Low Set
1 1 0.005s F 200Hz
Sample Calculation
Time High, Time Low Set 3. Since there are 2 variables in the TL equation, select C: C=10F
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Sample Calculation
Time High, Time Low Set
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Calculations: Astable
Frequency, Duty Cycle Set
(R A R B ) DC (R A 2R B ) F 1 0.693 (R A 2R B ) C
Notes: The value 0.693 is a factor associated with the charge/discharge cycle of the 555 timer.
Sample Design
Frequency, Duty Cycle Set
Build an oscillator using a 555 timer with a frequency of 72kHz at 75% D.C. Use a 100F capacitor.
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Design Solution
Frequency, Duty Cycle Set
Design Solution
Frequency, Duty Cycle Set
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Design Solution
Frequency, Duty Cycle Set
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Design Solution
Frequency, Duty Cycle Set
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Astable Configuration#2
Rb must be < .5 Ra
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Astable Configuration #3
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Comparator
The comparator is an operational amplifier (opamp) configuration. The comparator compares 2 analog voltages and provides a digital output.
If V+ > V-, the output is a digital 1 If V- > V+, the output is a digital 0
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Charge Animation
Discharge Animation
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Specification sheet
From the specification sheet for the LM555, determine the following:
Operational voltage range Maximum current output for each state Frequency Range Output rise and fall time
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Design Exercises
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Design Exercises
1. Using a 555 timer, design an oscillator with an output of 6Hz with a duty cycle of 60%. Use a 100F capacitor. Build in EWB.
2. Using a 555 timer, design an oscillator with an output of 10KHz with a duty cycle of 50%. Use a 3.3F Capacitor. Build in EWB.
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Animated Slides
The following slides contain animations to demonstrate the operations of: 555 as an astable: charge cycle 555 as an astable: discharge cycle
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+< >0 1
1 0 -< >+
0 1
1 0 Vc
Capacitor Charges via Ra and Rb Latch in a set state Q is low; Q output is high Capacitor continues to charge Lower comparator provides logic Upper comparator + input is Latch receives a reset state Q is high; Q output is low Transistor is on and a connection Capacitor begins to reference discharge low. Latch in hold state. greater than 2/3 Vcc to ground is made. Animated charge cycle
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-> <+
1 0 0 1 >+< 10
1 0
Vc
Capacitor is discharging. Q output Upper comparator + voltage less Latch in a hold state. Lower comparator + voltage is Latch is set. Q is low. is low. Q output is high. than reference Transistor is off. Capacitor greater than voltage. voltage. begins to charge. Animated discharge cycle
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END
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