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4143 Microcontrollers

Introduction

Lecturer: Dr Esam Al_Qaralleh


qaralleh@psut.edu.jo

Web Resources
Course: http://psut.edu.jo/sites/qaralleh Text book:
Designing Embedded Systems with PIC Microcontrollers (principles and applications), 1st Ed. By: Tim Wilmshurst published by Newnes, 2007.

http://www.elsevier.com/wps/find/bookdescription.c ws_home/708502/description#toc

What is a Microcontroller?
Mini-Computer
Microprocessor
The Brains Arithmetic Logic Unit (ALU) Control Unit

Program/ Data Storage Peripherals (Input/Output) Low-Cost

PIC Architecture

Memory

CPU

I/O (Ports A, B & C)

Timer 0

Timer 1

Timer 2

PWM 1

PWM 2

10-bit A/D USART

A Computer on a chip

Microcontroller Families

PIC 18F452 Architecture

PIC 18F452 General Architecture

PIC 18F452 : Peripherals


The PIC 18F452 has the following peripherals:
Data ports:
A (6-Bits) B, C and D (8-Bits) E (3- bits)

Counter/Timer modules.
Modules 0,2 (8-Bits) Modules 1,3 (16-Bits)

CCP Modules. I2C/SPI serial port. USART port. ADC 10-bits with 8-way input multiplexer. EEPROM 256 Bytes

Reset
A reset puts the PIC in a well-defined initial state so that the processor starts executing code from the first instruction. Reset can results from :
External reset by MCLR pulled down. Reset on power-up Reset by watchdog timer overflow Reset on power supply brown-out

Reset will cause all current data to be lost.

Microprocessor Unit
Includes Arithmetic Logic Unit (ALU), Registers, and Control Unit

Arithmetic Logic Unit (1 of 3)


The CPU fetches instructions from memory, decodes them, and passes them to the ALU for execution. The arithmetic logic unit (ALU) is responsible for adding, subtracting, shifting and performing logical operations. The ALU operates in conjunction with:
A general purpose register called W register And f register that can be any location in data location Literal embedded in the instruction code

Arithmetic Logic Unit (1 of 3)

Example ADDWF F, d, a

;Add WREG to File (Data) Reg. ;Save result in W if d =0 ;Save result in F if d = 1

Registers
Bank Select Register (BSR)
4-bit register used in direct addressing the data memory

File Select Registers (FSRs)


16-bit registers used as memory pointers in indirect addressing data memory

Program Counter (PC)


21-bit register that holds the program memory address while executing programs

Memory

PIC18F - Address Buses


Address bus
21-bit address bus for program memory addressing capacity: 2 MB of memory 12-bit address bus for data memory addressing capacity: 4 KB of memory

Data Bus and Control Signals


Data bus
16-bit instruction/data bus for program memory 8-bit data bus for data memory

Control signals
Read and Write

PIC18F452/4520 Memory
Program memory with addresses (Flash) Data memory with addresses

FFF=212=16x256=4096=4K

Program Memory
The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h.
A 21-bit program counter is capable of addressing the 2Mbyte program memory space.

PIC18F452 each have 32 Kbytes of FLASH memory. This means that it can store up to 16K of single word instructions

Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all 0s (a NOP instruction).

Data Memory Organization


000h 07Fh

Access RAM Bank 0 GPR

Data Memory up to 4k bytes Divided into 256 byte banks Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected

080h 0FFh 100h

PIC16F8F2520/4520 Register File Map

Bank 1 GPR
1FFh 200h

Bank 2 GPR
2FFh

Access Bank Access RAM Access SFR


00h 7Fh 80h FFh

D00h

Bank 13 GPR
DFFh E00h

256 Bytes

Bank 14 GPR
EFFh F00h F7Fh F80h FFFh

Bank 15 GPR Access SFR

Data Memory with Access Banks


GPR=General Purpose Reg. SFR=Special Function Reg. These registers are always accessible regardless which bank is selected acting as a virtual memory -

Data Memory also known as Register File We will discuss the access to every region later, while talking about PIC18 instructions

FFF=212=16x256=4096=4K

Accessing Data Memory


The machine code for a PIC18 instruction has only 8 bits for a data memory address which needs 12 bits. The Bank Select Register (BSR) supplies the other 4 bits.

Data Memory Addressing


Direct Addressing - Operand address(es)

embedded in the opcode


8 bits of the 16-bit instruction specify any one of 256 locations The 9th bit specifies either the Access Bank (=0) or one of the banks (=1)

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Data Memory Addressing


Direct Addressing Examples
Direct addressing (banked)
movlb 02 ;set BSR to Bank 2 addwf 0x55, W, BANKED ; add WREG with the content of ; addr. 55 (f=55) in bank 2 (a=1), ; save the result to WREG (d=0) Operand is the content of data memory at add. 0x255 Mnemonic in MPASM: A (a=0) - the access bank; BANKED (a=1) - banked W (d=0) - the WREG register; F (d=1) - the data register
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Data Memory Addressing


Direct Addressing Examples
Direct addressing (using access bank)
addwf 0x55, F, A ;movlb not required ; add WREG to content of ; addr. 55 (f=55) in access ; bank (a=0), save the result ; in the data memory at the ;address 0x55 (d=0)

Operand is the content of data memory add. 0x055


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Data Memory Addressing


Indirect Addressing 3 File Select Registers (FSR) as a pointer to the data memory location that is to be read or written.

Each FSR has an INDF register associated with it The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register.

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Data Memory Addressing


Indirect Addressing

LFSR 02, num1 ;load FSR2 with the add. of num1 MOVWF INDF2, W ; move WREG to the register ; pointed by FSR2

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Data Memory Addressing


Indirect Addressing Operations

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Data Memory Addressing


Indirect Addressing Example
count set 0x02 lfsr 0, num1 lfsr 1, num2 movlw 3 movwf count, A bcf STATUS, c Again: movf POSTINC1, W addwfc POSTINC0, F decfsz count, 1 bra Again

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SFRs Examples

I/O Ports

PIC18F452 I/O Ports


Five I/O ports
PORT A through PORT E Most I/O pins are multiplexed Generally have eight I/O pins with a few exceptions Addresses already assigned to these ports in the design stage Each port is identified by its assigned SFR

Parallel I/O Output Structure

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Parallel I/O Input Structure

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Parallel I/O Combined I/O Structure

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Parallel I/O ports Main Features


Simple memory mapped access Can be configured through software as either input or output Ability to set or reset individual bits Can have internal pull-ups Can drive small loads like LEDs Can be multifunction Different capability for pins (i.e. larger current)
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Parallel I/O ports


For most ports, the I/O pins direction (input or output) is controlled by the data direction register TRISx (x=A,B,C,D,E): a 1 in the TRIS bit corresponds to that pin being an input, while a 0 corresponds to that pin being an output The PORTx register is the latch for the data to be output. Reading PORTx register read the status of the pins, whereas writing to it will write to the port latch. Example: Initializing PORTB (PORTB is an 8-bit port. Each pin is individually configurable as an input or output). bcf STATUS, RP0 ; select bank0 bcf STATUS, RP1 clrf PORTB ; clear PORTB output data latches bsf STATUS, RP0 ; select bank1 movlw 0xCF ; value used to initialize data direction movwf TRISB ; PORTB<7:6>=inputs, PORTB<5:4>=outputs, ; PORTB<3:0>=inputs
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Relationship between TRIS and PORT Registers

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Illustration: Displaying a Byte at an I/O Port (1 of 5)


Problem statement:
Write instructions to light up alternate LEDs at PORTC.

Hardware:
PORTC
bidirectional (input or output) port; should be setup as output port for display

Logic 1 will turn on an LED in Figure 2.10.

Illustration (2 of 5)TRISC=0
Interfacing LEDs to PORTC Port C is F82H Note that PORT C is set to be an output! Hence, TRISC (address 94H) has to be set to 0

Illustration (3 of 5)
Program (software)
Logic 0 to TRISC sets up PORTC as an output port Byte 55H turns on alternate LEDs
MOVLW 00 ;Load W register with 0 MOVWF TRISC, 0 ;Set up PORTC as output MOVLW 0x55 ;Byte 55H to turn on LEDS MOVWF PORTC,0 ;Turn on LEDs SLEEP ;Power down