Architecture of 8086

Basheer V P Asst. Professor Department of Electronics and Communication Engineering A Ameen Engineering College

Internal Architectureof 8086

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Internal Architecture -Introduction

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Internal Architecture -Introduction

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Execution Unit
Introduction

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Control System
Control system consists of instruction decoder and control unit. The function of instruction decoder is to decode the fetched instructions. Function of control unit is to generate the control signals.

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ALU
ALU is the heart of the processor. 8086 has a 16- bit AlU. AlU is capable to operate 16 bit operands. All the arithmatic and logical operations are performed by ALU.

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General Purpose Registers

AX
Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operations
BX
-BX is known as Base Register. -Also serves as address register.
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Pointer registers
Two pointer registers Stack Pointer (SP) and Base Pointer (BP) are used to access data in the stack segment. SP and BP are 16 bit registers used to hold the offset address of stack segment. Any one of this register provides an offset value which associated with the SS register, refers to the current word being processed in the stack.
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Index registers
Source Index (SI) is a 16 bit register used to hold the offset address of data segment. Destination Index (DI) is also a 16 bit register used to hold the offset address of extra data segment. Index registers are used as default memory pointers in string operations.

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Bus Interface Unit (BIU)

Introduction.

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Introduction contd..

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Instruction Queue
Instruction Queue is FIFO group of registers. Size is 6 bytes. Dedicated element for pipelining. Used to store pre-fetched the instructions while EU executing some other instruction. 6 bytes of instruction code can be pre-fetched i. this queue.

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Segment Registers

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 Code Segment Register

CS is a 16-bit register used to store the base address of the code segment. This segment address , plus an offset value in Instruction Pointer (IP) register (CS:IP),indicates the address of an instruction to be fetched.

Data Segment Register

DS is a 16-bit register used to store the base address of the data segment. This segment address , plus an offset value in SI register (DS:SI),indicates a specific byte location in the data segment.
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 Stack Segment Register

SS is a 16-bit register used to store the base address of the stack segment. This segment address , plus an offset value in Stack Pointer (SP) register (SS:SP),indicates the current word in the stack being addressed.

Extra data Segment Register

ES is a 16-bit register used to store the base address of the extra data segment. This segment address , plus an offset value in DI register (ES:DI),indicates a specific byte location in the extra segment.
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Instruction Pointer (IP)

IP is used to hold the offset address of code segment. The Instruction Pointer identifies the location of the next word of the instruction code to be fetched.

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Address Generation Unit

Function is to generate 20-bit physical address. Physical address is obtained by shifting the segment address 4 bits to the left (inserting 4 zeros at the right) and adding the offset address.

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Pipelined architecture of the 8086 microprocessors

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