1

BACKEND TECHNOLOGY Chapter 11

Introduction
Backend technology: fabrication of interconnects
and the dielectrics that electrically isolate them.
Early structures were simple by today's standards.
Oxide
Silicon
Aluminum
N
+
Oxide
More metal interconnect levels
increases circuit functionality and
speed.
Interconnects are separated into
local interconnects (polysilicon,
silicides, TiN) and intermediate/
global interconnects (Cu or Al).
Backend processing is becoming
more important.
Larger fraction of total structure
and processing.
Starting to dominate total speed
of circuit.
(From ITRS)
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
Upper Saddle River NJ
2

3
Back-End Technology
Al Cu
silicides
BACK END
TECHNOLOGY
(Back Of Line)
Front End
Technology
Gate & Local interconnects will give delay with scaling
global interconnects will delay !
4
METAL 2
METAL 1 METAL 1
W VIA
POLYCIDE
W CONTACT
Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018
Technology N ode (half pi tch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
Min Metal 1 Pitch (nm) 214 152 108 76 54 42
Wiring Levels - Logic 10 11 12 12 14 14
Me tal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0
Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20
STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4
Me tal Resistivi ty (ohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7
Back-End Technology_ Dimensions
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
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2000 by Prentice Hall
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Interconnects
scaling
larger X-sections, thicker dielectrics
Global inter.
delay
usually 200 - 350 mm
2

C of adjacent lines C line to substrate
RC delay
For min feature size F
min

3 -5 nsec
F
min

AP (A
intercon
R & C
diel

with chip area
-
l
W
P
o
l
y
1 10 100
F
min
= 0.25 m
t
g
10
10
10
-10
10
-9
10
-8
-12
-11
A
l
W
P
o
l
y
1 10 100
F
min
= 0.5 m
t
g
Poly
(

= 5 0 0
O
c m )
WSi
2
(

= 3 0
O
c m )
W
(

= 1 0
O
c m )
Al
(

= 3
O
c m )
1 10 100
F
min
= 1 m
t
g
D
e
l
a
y

T
i
m
e

(
s
e
c
)
Chip Area (mm
2
)
C
u
t L
t L
t L
W
S
i 2
W
S
i 2
A
l
The speed limitations of interconnects can be estimated fairly simply.
The time delay (rise time) due to global
interconnects is:
Dielectric constant
of the oxide K
ox

K
1
- accounts for
the fringing fields
Gate
delay
Ex. =3e-6cm, c
SiO2
=3.9, A=100mm
2
,

F
min
=0.35m
t
L
=0.75ns (increases with chip A due to R)
Global delay increases
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Scaling: Contacts & Interconnects

Global
Global
Self - aligned
Self - aligned
Self - aligned
50% delay from interconnects
Earlier:15-20%, then 30-40%
(delay increases with scaling)
7
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
Upper Saddle River NJ
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More sophisticated analysis from
the 2003 ITRS interconnect roadmap.
Global interconnects dominate
the RC delays.
In the long term, new design or
technology solutions (such as
co-planar waveguides, free space
RF, optical interconnect) will be
needed to overcome the
performance limitations of
traditional interconnect. (ITRS)
Historical Development and Basic Concepts
Contacts
Oxide
Silicon
Aluminum
N
+
Oxide
Early structures were simple Al/Si contacts.
Highly doped silicon regions are necessary to insure
ohmic, low resistance contacts.

c
=
co
exp
2|
B
m
*
c
s
N
D
|
\


|
.
|
|
(2)
Tunneling current through a Schottky barrier
depends on the width of the barrier and hence N
D
.
In practice, N
D
, N
A
> 10
20
are required.
Delay Due to Metal 1 and Global
SILICON VLSI TECHNOLOGY
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2000 by Prentice Hall
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Aluminum Metallization
high compressive stress in Al during annealing
large
All silicides give self-aligned
contacts contact area R
passive
Al contact: SiO
2
native reduced
good ohmic! Al
2
O
3
forms, very stable adhesion to SiO
2

0 + +
C
Add Si 1%toAl, Si can precipitate (450 C) p (Si +Al) R (for n layers)
USE BARRIERS INSTEAD
|

Q
it

during
annealing
@ 450
0
C
H formation
High SS of Si in Al 0.5% 450
0
C
High Si diff
in Al
SPIKES!
in local spots

Al - 2-3 m
junctions
only!
Ti as a
sacrificed
Barrier
TiSi
2
&
TiN
(=diffusion
barrier)



Better solution
10
Contacts - Electrical Parameters
thermionic emission
Schottky = rectifying
Tunneling
Surface states in Si pin
F-level deep in the E-gap
no metal gives |
B

for n Si contact
resistance & rectifying
contact
thermionic emission
Tunneling
contact
Thickness of
depletion =
tunneling layer
2.5 nm
results from
N
d
=6. 10
19
cm
-3
contact area
-3
-3
B
-7 2
C
-2 2
C 19
10 cm
-6 2
C 20
10 cm
o
ex : = 0.6V
=10 cm
| = 5.9.10 cm
| = 6.7.10 cm
ROLE OF CONCENTRATION
Depends on metal/semiconductor
R
c
[]=[cm]/A[cm
2
]

c
|10
19
cm
-3
=5.910
-2
cm
2

c
|10
20
cm
-3
=6.710
-6
cm
2

c
10
-9
cm
2
will
be needed

Role of concentration
11
Silicides and Polycides
gate
contacts
local interconnects (require a-Si deposition)
SALICIDE PROCESS
sputtering
T (~ 600
0
C )
C 49 Ti Si
2
- high resistive
T ( > 800
0
C )
C 54 Ti Si
2
- low resistive
Larger grains

Ti also against electromigration
12
Silicides
Good
adhesion
Problems :
adhesion
stability

stress
large
SILICON CONSUMPTION
striped
CoSi
2
does not cause
problems with resistivity
for very narrow lines
13
Some front-end models have also been applied to back-end processing.
Silicide formation is often
modeling using the Deal-Grove
linear-parabolic model.


x
s
2
B
+
x
s
B / A
= t +t or
x
s
=
A
2
1+
t +t
A
2
/ 4B
1






`

)

(7)

-0.8 -0.4 0.0 0.4 0.8

y in microns
-0.4
-0.2
0
0.2
0.4
x

i
n

m
i
c
r
o
n
s
Silicon
Titanium
Polysilicon
Silicon
dioxide
Oxide
spacer
m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m
x

i
n

m
i
c
r
o
n
s
Silicon
Titanium Titanium silicide
Titanium
nitride
Titanium
silicide
Silicon
dioxide
Pinning point
-0.8 -0.4 0.0 0.4 0.8
y in microns
-0.4
-0.2
0
0.2
0.4
Simulation of TiSi
2
formation using FLOOPS [11.32] on a 0.35 m wide gate
structure. Left: before formation anneal step. Right: after formation anneal
step: 30 sec at 650C in a nitrogen atmosphere
TiSi
2
Salicide Formation
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
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2000 by Prentice Hall
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TiSi
2
Salicide Formation
Si is the diffuser
for CoSi
2
TiSi
2

Creep - up
short G - S
Less lateral encroachment
Consumption of Silicon Large :
Ti Si
2
= 138 nm from Ti = 55 nm
Si consumed = 125 nm
fast diffusion
Linear coefficient
= fast reaction
conductive
Growth as in the oxidation
process: parabolic and linear
15
Silicide Formation and Scaling of
Devices
650
0
C/ 30

Ar

@ the top of the oxide spacer
TiN growth:
20% of TiSi
2
linear
growth rate
32.5 nm Ti
44 nm Si
50 nm TiSi
2
+
27 nm TiN
Not all Ti consumed
See Deal & Grove
Linear / Parabolic
growth
Anneal now in N
2

2 widegate m
2m wide channel
0.35m wide channel
48 nm TiSi
2

from 43 nm Si
Stress important: include
mechanical parameters
16
For 1 nm of metal (Ti, Co, Ni):
TiSi
2
- 2.27 nm Si used
CoSi
2
- 3.64 nm Si
NiSi -1.83 nm Si
17
18
Electrical Measurements of Contacts
gives
overestimation
( R
C
) of the
contact properties
Low resistance
KELVIN BRIDGE
19
Multilevel Metallization
Non planar surface :
(1) Lithography issues
depth of focus
resist thinning
UV light reflections

(2) Step coverage & filling
Use planarization
FINAL GOAL
FOR ADHESION &
DIFFUSION BARRIER
FOR ADHESION
Early two-level metal structure
(early 1980s). Non-planar
topography leads to lithography,
deposition, filling issues.
These issues get worse with
additional levels of interconnect
and required a change in structure.

20
Planarization
selective
deposition
GOOD PLANARITY BY FILLING VIAS
21
Degree of planarization is


DOP = 1
x
step
f
x
step
i
(3)
W plug
Oxide
Silicon or Al
TiN
Blanket W
Etchback W
One early approach to
planarization incorporated W
plugs and a simple etchback
process. (Damascene process.)
SPEEDIE simulation below.
-0.5
0. 0
0. 5
1. 0
1. 5
2. 0
-1.00 1. 00 0. 0
microns
m
i
c
r
o
n
s
-2.00 2. 00
2. 5
Planarization: definition and simulation
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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More advanced version of the
damascene process provides both the
via/contact and interconnect levels
simultaneously.
In this dual damascene process,
both the openings in the IMD for
the metal interconnect and for the
contact or vias underneath are
opened, one after the other.
Metal is then deposited into both
layers at once followed by a CMP
etchback.
Interconnects have also become multilayer structures.
Shunting the Al helps mitigate electromigration and
can provide mechanical strength, better adhesion and
barriers in multi-level structures. TiN on top also acts
as antireflection coating for lithography.
Planarization
Planarization Also Helps Against Electromigration
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Dielectrics
Local
Interconnects
Global
Interconnects
Vias
Contacts
Intermetal
Dielectric
First Level
Dielectric
Dielectrics electrically and
physically separate interconnects
from each other and from active
regions.
Two types:
- First level dielectric
- Intermetal dielectric (IMD)
BPSG
First level dielectric is usually SiO
2
doped
with P or B or both (2-8 wt. %) to enhance
reflow properties.
PSG: phosphosilicate glass, reflows at 950-1100C
BPSG: borophosphosilicate glass, reflows at 800C.
SEM shows BPSG oxide layer after 800C reflow
step, showing smooth topography over step.
Undoped SiO
2
often used above and below
PSG or BPSG to prevent corrosion of Al .
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Fundamentals, Practice and Modeling
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2000 by Prentice Hall
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ILM DIELECTRICS
BPSG used for planarization
25
Intermetal dielectrics also made primarily of SiO
2

today, but cannot do reflow or densification anneals
on pure SiO
2
because of T limitations.
Two common problems occur, cusping and voids,
which can be minimized using appropriate
deposition techniques.

-0.5
0.0
0.5
1.0
1.5
2.0
-1.00 1.00 0.0
microns
-2.00 2.00
2.5
microns
SPEEDIE simulations of silicon
dioxide depositions over a step
for silane deposition (S
c
= 0.4)
and TEOS deposition (S
c
= 0.1)
showing less cusping in the latter
case.
b) Local planarization
c) Global planarization
Oxide
a) No planarization
However planarization
is also usually required
today.
Planarization
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
Upper Saddle River NJ
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Silicon
Al
Metal 1
SOG
CV
DO
xide
Via Al - Metal 2
Silicon
AlM
etal 1
Al - Metal 2
Via SOG
CVD
Oxide
CVD
Oxide
SOG SOG
CVD
Oxide
CVD
Oxide
Al
Metal 1
Via
One simple process involves planarizing with
photoresist and then etching back with no
selectivity.
Spin-on-glass (SOG) is another option:
Fills like liquid photoresist, but becomes
SiO
2
after bake and cure.
Done with or without etchback (with
etchback to prevent poisoned via - no SOG
contact with metal).
Can also use low-K SODs. (spin-on-dielectrics)
SOG oxides not as good quality as thermal or
CVD oxides
Use sandwich layers.

A final deposition option is HDPCVD (see
chapter 9) which provides angle dependent
sputtering during deposition which helps to
planarize.

with etchback
without etchback
Planarization
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Planarization Techniques
Reflow
CMP appears as a dominating method
28
Wafer carrier
Wafer
Polishing pad
Polishing table
Slurry
(facing down)
Close-up of wafer/pad interface:
Polishing pad
(semi-rigid)
Silicon
Oxide
slurry
Deposit thick oxide
Plasma etchback
Locally planarized topography remains
CMP
Globally planarized topography remains
The most common solution today is
CMP which works very well.
It is capable of forming very flat surfaces
as shown in the example below.
CMP
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Typical modern interconnect
structure incorporating all
these new features.
The biggest change that has occurred in the past 5 years is the widespread
introduction of Cu, replacing aluminum.
Cu cannot be easily etched since the byproducts, copper halides are not volatile at
room temperature.
Electroplating (see text section 9.3.10) plus a damascene process (single or dual)
is the obvious solution and is widely used today.
Cu is the dominant material in logic chips today (p, ASICs), but not in most
memory chips.
Copper Interconnects
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
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2000 by Prentice Hall
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Backend structure showing one
possible dielectric multi-structure
scheme. Other variations include
HDP oxide or the use of CMP.
Two backend structures. Left: three metal levels and encapsulated BPSG for the
first level dielectric; SOG (encapsulated top and bottom with PECVD oxide) and
CMP in the intermetal dielectrics. The multilayer metal layers and W plugs are also
clearly seen. Right: five metal levels, HDP oxide (with PECVD oxide on top) and
CMP in the intermetal dielectrics.
Multilevel Metallization
2000 by Prentice Hall
Upper Saddle River NJ
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Interconnects And Vias
Al has historically been the dominant material for interconnects.
- low resistivity
- adheres well to Si and SiO
2

- can reduce other oxides
- can be etched and deposited easily

Problems: -relatively low melting point and soft.
-need a higher melting point material for gate electrode and local
interconnect polysilicon.
- hillocks and voids easily formed in Al.
Hillocks and voids form because
of stress and diffusion in Al films.
Heating places Al under
compression causing hillocks.
Cooling back down can place Al
under tension voids.
Adding a few % Cu stabilizes
grain boundaries and minimizes
hillock formation.
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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A related problem with Al interconnects
is electromigration. High current density
(0.1-0.5 MA/cm
2
) causes movement of
Al atoms in direction of electron flow.
Can cause hillocks and voids, leading to
shorts or opens in the circuit.
Adding Cu (0.5-4 weight %) can also
inhibit electromigration.
Thus Al is commonly deposited with
1-2 wt % Si and 0.5-4 wt % Cu.
Next development was use of other materials
with lower resistivity as local interconnects,
like TiN and silicides.
Silicides used to 1. strap polysilicon, 2. Strap
junctions, 3. as a local interconnect.
Electromigration
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Mechanical Properties of Al
protrusion of Al
Al short
Si O
2
may crack
heating
HEATING :
Large thermal expansion coefficient
compressive stress hillock shorts
Add Cu Al diffusion by segregating
@ the Al grain boundary

COOLING : void formation
Cu helps again Al diffusion


agglomeration of Al atoms
Grain boundary
diffusion
0.1 0.5 mAcm
-2

ELECTROMIGRATION ---
depends on grain structure & size
Cu helps - 4 wt % (avoid corrosion &
etching problems )
Si added helps EM but PR
34
Electromigration
35
Electromigration
36
Grain Growth
37
THE FUTURE OF BACKEND TECHNOLOGY
t
L
= 0.89RC = 0.89 K
I
K
ox
c
o
L
2
1
Hx
ox
+
1
WL
S
|
\

|
.
|
Remember:
(1)
Reduce metal resistivity - use Cu instead of Al.
Aspect ratio - advanced deposition, etching and planarization methods.
Reduce dielectric constant - use low-K materials.
Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018
Technology N ode (half pi tch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
Min Metal 1 Pitch (nm) 214 152 108 76 54 42
Wiring Levels - Logic 10 11 12 12 14 14
Me tal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0
Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20
STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4
Me tal Resistivi ty (ohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Material class Material Dielectric
constant
Deposition
technique
Inorganic SiO
2
(including PSG
and BPSG)
3.9-5.0 CVD/Thermal
ox./Bias-
sputtering/HDP
Spin-on-glass (SiO
2
)
(including PSG, BPSG)
3.9-5.0 SOD
Modified SiO
2
(e.g. fluorinated SiO
2
or hydrogen
silsesquioxane - HSQ)
2.8-3.8 CVD/SOD
BN (Si) >2.9 CVD
Si
3
N
4
(only used in
multilayer structure)
5.8-6.1 CVD
Organic Polyimides 2.9-3.9 SOD/CVD
Fluorinated polyimides 2.3-2.8 SOD/CVD
Fluoro-polymers 1.8-2.2 SOD/CVD
F-doped amorphous C 2.0-2.5 CVD
Inorganic/Org-
anic Hybrids
Si-O-C hybrid
polymers based on
organo-silsesquioxanes
(e.g. MSQ)
2.0-3.8 SOD
Aerogels
(Microporous)
Porous SiO
2
(with tiny
free space regions)
1.2-1.8 SOD
Air bridge 1.0-1.2
All of these approaches are beginning to appear in advanced process flows today.
Inter Level Dielectrics
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
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Summary of Key Ideas
Backend processing (interconnects and dielectrics) have taken on increased
importance in recent years.

Interconnect delays now contribute a significant component to overall circuit
performance in many applications.

Early backend structures utilized simple Al to silicon contacts.

Reliability issues, the need for many levels of interconnect and planarization
issues have led to much more complex structures today involving multilayer
metals and dielectrics.

CMP is the most common planarization technique today.

Copper and low-K dielectrics are now found in some advanced chips and their
use will likely be common in the future.

Beyond these materials changes, interconnect options in the future include
architectural (design) approaches to minimizing wire lengths, optical
interconnects, electrical repeaters and RF broadcasting. All of these areas will see
significant research in the next few years.
SILICON VLSI TECHNOLOGY
Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall
Upper Saddle River NJ