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Class D Power amplifier

-----using ADS
Song lin @utk June30

Outline
Why select Class D?
Compare different device
Simple Class D architecture
Load-pull to give out Zout
Matching and simulation results of ideal
narrow band Class D PA
Broad band matching

Why Class D?
Class D PA works in the switching mode, with a
square wave voltage and a half wave rectified sine
wave of current.
In its ideal switching mode,
when Vds<>0, Ids=0;
when Ids<>0,Vds=0.
Class D PA can achieve very high frequency close to
100%. Although it is very nonlinear, we still can use
the LINC technique to kill the IMD product.

Two kinds of Class D PA

Compare the device(I)


For high frequency, ----- f m ax the higher the better
For high on/off switching speed,----- t sd the shorter
the better
For high efficiency, the on-resistance of a switching
device must be as low as possible to minimize the
power dissipation in the switches during the positive
half cycle.----- Rs is the smaller the better.
For high Power output, ----- BV(beake down voltage)
the higher the better
For high Gain, ----- g m the bigger the better
For power dissipate,----- I ds the small the better

Compare the device(II)


Conclusion:

Also for the wide band application, we should chose the


component whose Zout and Zin has very little variety
in some frequency range.
I suggest to use the MRF282SR1.-----N-channel
Enhancement-Mode Lateral MOSFETs

Basic Class D PA architecture

Load Pull to give out Zout

Narrow band input and output matching


and simulation results
1.5
1.0

ts(vin), V

0.5
0.0
-0.5
-1.0
-1.5
0.0

0.5

1.0

1.5

2.0

2.5

2.0

2.5

time, nsec
6

ts(voad), V

4
2
0
-2
-4
-6
10

ts(ID_FET2.i), A
ts(vds2), V

ts(ID_FET1.i), A
ts(vds1), V

0.0
10

6
4
2
0

6
4
2

-2
0.0

0.5

1.0

1.5

time, nsec

2.0

2.5

1.0

1.5

time, nsec

-2

0.5

0.0

0.5

1.0

1.5

time, nsec

2.0

2.5

Wide band matching using coaxial

freq

A conventional design allows the coaxial


transformer to transform the impedance
to obtain a match the low end of the
band, then add additional low-pass
matching sections to lower the
impedance at the upper band edge.

30.00MHz
80.00MHz
130.0MHz
180.0MHz
230.0MHz
280.0MHz
330.0MHz
380.0MHz
430.0MHz
480.0MHz
530.0MHz
580.0MHz
600.0MHz

Zin1
12.879 + j1.508
11.948 - j1.362
10.330 - j1.846
9.075 - j1.320
8.380 - j0.381
8.217 + j0.612
8.497 + j1.406
9.052 + j1.766
9.545 + j1.536
9.520 + j0.857
8.775 + j0.239
7.597 + j0.117
7.105 + j0.224

Using the MRF282S to simulate narrow


band VMCD @300MHz

Push_pull structure

Narrow band matching (input, output)

Narrow band simulation results


DC Power Calculations
The exists() function checks to be sure
the corresponding piece of data is in
the dataset. If it is not, then the
function returns 0.

Power Delivered and Power-Added


Efficiency Calculations
Eqn Pdel_Watts=real(0.5*vout[1]*conj(Iload.i[1]))
Pavs is the available source power, set on
the schematic, and passed into the dataset
using the Harmonic Balance controller.

Eqn Vs_l=exists("real(Vs_low[0])")
Eqn Vs_h=exists("real(Vs_high[0])")
Eqn Is_h=exists("real(Is_high.i[0])")

Eqn Pavs_Watts=10**((28-30)/10)
Eqn PAE=100*(Pdel_Watts-Pavs_Watts)/Pdc

Eqn Is_l=exists("real(Is_low.i[0])")

Eqn Pdel_dBm = 10*log10(Pdel_Watts)+30

Eqn Pdc=Is_h*Vs_h +Is_l*Vs_l +1e-20

Pdel_Watts
36.194

40

30
2
20
1
10
0

0
-10

-1
0

time, nsec

45.112

Pdel_Watts/Pdc
0.802

50

40

30
2
20
1
10
0

0
-10

-1
0

time, nsec

ts(ID_FET2.i), A

50

Pdc

ts(ID_FET1.i), A

ts(vds1), V

78.833

ts(vds2), V

PAE

Final schematic

Final simulation results(1)


RFfreq
0.01000
0.03034
0.05069
0.07103
0.09138
0.11172
0.13207
0.15241
0.17276
0.19310
0.21345
0.23379
0.25414
0.27448
0.29483
0.31517
0.33552
0.35586
0.37621
0.39655
0.41690
0.43724
0.45759
0.47793
0.49828
0.51862
0.53897
0.55931

eta
3.18477
19.17149
26.69007
33.87357
38.05973
40.55221
52.89915
61.16288
63.58578
65.09090
69.37040
71.57224
74.12389
73.81647
71.28339
72.02632
76.89164
76.92763
75.85785
78.19259
80.02783
79.86804
79.41265
80.30537
82.43311
83.18813
81.66282
80.91020

Pdc
35.42361
45.42576
41.53192
53.37189
50.67507
47.00999
57.24243
62.92600
59.01689
54.75491
53.13651
50.51480
49.14442
48.24101
45.85446
44.49014
44.81067
45.92195
47.14371
48.25363
47.38484
47.11465
46.80491
45.77380
43.78908
41.57842
40.07803
39.06156

Pdel_Watts
1.12816
8.70879
11.08490
18.07896
19.28679
19.06359
30.28076
38.48735
37.52635
35.64047
36.86101
36.15457
36.42776
35.60981
32.68661
32.04461
34.45566
35.32667
35.76221
37.73077
37.92106
37.62955
37.16902
36.75882
36.09670
34.58831
32.72885
31.60478

PAE
-10.96363
8.13838
14.62255
24.48310
28.16952
29.89092
44.14363
53.19817
55.09351
55.93762
59.93833
61.65064
63.92564
63.42723
60.35343
60.76119
65.70708
66.01374
65.22680
67.80608
69.45087
69.23043
68.70464
69.35615
70.98762
71.13411
69.15753
68.07950

Gain
-6.47623
2.39960
3.44730
5.57170
5.85255
5.80199
7.81161
8.85313
8.74332
8.51940
8.66565
8.58163
8.61434
8.51572
8.14374
8.05760
8.37266
8.48109
8.53431
8.76702
8.78887
8.75535
8.70186
8.65366
8.57471
8.38932
8.14932
7.99753

Final simulation results(2)


60

2
1
0

20

-1
-2

ts(I_ds.i), A

ts(vd1), V

40

0
-3
-20

-4
0

time, nsec
eta
73.76255

Pdc
42.70324

Pdel_Watts
31.49900

PAE
62.02603

Gain
7.98301

The problem remain:


1. The Class D PA need a resonator tank to pull out the

2.

3.

4.

fundamental signal, to filter out the third time signal, so


I decide to divide the band into 3 parts, one from 30 to
88 MHz; 88MHz to 200MHz; 200MHz to 500MHz. We
can separate the signals by filter bank.
For the real device, the Rs isnt very small, so the
efficiency cant be so high. Because of the t ds , the Vds
and some overlap with Ids, it also kill some efficiency.
To achieve better performance at low frequency band, I
have to increase the Vgg.
ADS is very hard to converge when simulation.

Thank you!!!