Understanding and Protecting Against Electrical Overstress (EOS) of Operational-Amplifiers

By Thomas Kuehl Senior Applications Engineer Precision Analog Linear Applications Engineering

This is your IC

This could be your IC after an electrical overstress event!

Presentation Subjects

ESD and EOS definitions

Amplifier input range

ESD models Internal ESD and consequently EOS protection circuits Amplifier EOS operating situations External EOS protection

ESD and EOS: Whats the difference?

Electrostatic Discharge (ESD) The transfer of electrostatic charge

between bodies or surfaces at different electrostatic potential.

Electrical Over Stress (EOS) The exposure of an item to current or voltage beyond its maximum ratings.

ESD High voltage (kVs) Short duration event (1-100ns) Fast edges Low power Out of circuit event

EOS Low voltage >Vs Longer duration event Low power In-circuit event

Two very different environments

Handling and assembly environments

ESD

PC Board

EOS
-5V bus
V1 5 L1 50n C1 100n R2 10k OP2 !OPAMP Vout + C2 100n R4 1k

R1 1k OP1 !OPAMP 10V

0V

+ VG1 R3 1k L2 50n

+5V bus
V2 5

The TI data sheet Absolute Maximum Ratings is a good place to check and assure EOS problems are avoided

Input voltage range of an op-amp

+
+2kV +100V +5.5V +5.0V +3.5V
Rs 1k

ESD protect region

Safe with Rs Non-linear input

In-circuit max positive Pos Safe Pos rail

OPA735 low Drift CMOS Op-amp

-

U1 OPA735 Vo
+

*
+

Input voltage

CMV input range 0V -0.1V -0.5V Safe with Rs -5.0V -100V ESD protect region -2kV Neg rail Neg safe
Vi 2.5

C1 100n

V1 5

In-circuit max negative

* Selected to limit input current to 10mA max.

ESD Stress Models

R1 1.5k

L1 7.5u

VG1

ESD model Human Body Model Machine Model Charged Device Model HBM MM CDM

R 1.5 k 20 20

C1 100p

d (i) R * di 1 * i 0 2 L dt LC dt

L 7500 nH 750 nH 5 nH

C 100 pF 200 pF 2-10pF

V 2kV 100 - 200V 200V - 1kV

Human Body model

Human Body ESD Model modeled in TINA Spice

IC1

DUT
R1 1.5k SW1 t C2 2p Rdut 10 VF1

2kV

IC L1 7.5u

C1 100p

1.5 1.0

AM1

AM1 (Amps) 500.0m

Rdut = 10 Ohms
0.0 15.0 10.0 VF1 (Volts) 5.0 0.0 0 50n 100n Time (s) 150n 200n

Rdut is the on resistance of an ESD protection circuit

Machine Model
Machine ESD Model modeled in TINA Spice
IC1

DUT
R1 10 SW1 t C2 2p Rdut 10 VF1

200V

IC L1 500n

C1 200p

4.0

Rdut = 10 Ohms
2.0 AM1 (Amps) 0.0 -2.0 40.0 20.0 VF1 (Volts) 0.0 -20.0 0 50n 100n Time (s) 150n 200n

AM1

Rdut is the on resistance of an ESD protection circuit

CDM - ESD by induction

T 400

Cp: 2p[F] Cp: 4p[F] Cp: 6p[F]

200

Charge Device Model modeled in TINA Spice

IC1 IC L1 5n R1 20 SW1 VF1

Voltage (V)
0
VG1

250V
-200

C1 10p 2 - 10pF

Rdut 10
T 5.0

0.0

1.0n

2.0n Time (s)

3.0n

4.0n

Cp: 6p[F]

Cp 2p
2.5

Cp: 4p[F] Cp: 2p[F]

Rdut is the on resistance of an ESD protection circuit

AM1

Current (A)

0.0

-2.5

-5.0 0.0 1.0n 2.0n Time (s) 3.0n 4.0n

Common input/output ESD protection circuits

Input steering diodes

Vdd / Vcc bus

CMOS input/output protection

output pad
Ouput Pad

R4 19.5

Pad

V+

C1 20f
D2 1N914 D1 1N914

Pad/Pin

R2 74 R1 190

Input Pad

-Vdd / Vee bus

R3 74

Pad

Vcer input clamp

R1 1k T4 !NPN D3 1N914

C1 20f V-

SCR

C1 20f V-

Rb

D1 PMLL4448 T1 Noname D2 PMLL4448 T1 Noname

IC level SCR model is more complex

Vee

R4 10.2

input or output circuit

R4 9.4

R4 9.4

R4 9.4

R4 9.4

R4 9.4

R4 9.4

Absoption circuit

OR

input pad

Supply clamp circuits

Bipolar BVcer Clamp

V+ IS1 1u

NPN bipolar
on high-speed process

Avalanche generating current - internal or external source

T1 !NPN RB 500 V-

RB set by design and process

NMOS Clamp
V+ V+

NMOS parasitic NPN transistor

T2 Noname RB 500 V-

V-

T3 !NPN Rsub 500

ON OFF

NMOS parasitic bipolar transistor

Drain (collector)

Gate

Source (emitter)

IDS IC Isub Rsub

n
p

Sub (base)

P-sub/epi

A commonly applied ESD protection method for analog integrated circuits

Input protection
D1 1N4148
ultra low leakage diodes

V+

Output protection

D3 1N4148

Rs 1k In+

+ IOP1

D5 1N4148

Vo

D6 1N4148

D2 1N4148

Rs 1k

D4 1N4148

In-

T1 !NPN

Rb 2k

V-

Power supply absorption device

INA168 ESD cell layouts

Input pin
ESD2 N-sinker BL ESD1 NPN B-E

Supply clamp

NPN transistor / resistor

Output pin
ESD7 NPN B-E ESD8 N-sinker BL

The ESD protection paths

V+ pin at GND
V+

D1 1N4148

D3 1N4148

D5 1N4148

In+

Rs 1k

Vout at GND
Vo T1 !NPN

+ IOP1

+
VG1

D2 1N4148

Rs 1k

D4 1N4148

D6 1N4148

In-

ESD pulse source

Rb 2k

V-

V- pin at GND

Input overdrive may activate ESD protection circuits

VG2 unintended transients, noise impulses, etc.

Vin+
-

V-

U1 OPA364

2.25 0.00 -2.25 1.00

VG1

TL1
+

Vo
+

VG2

V+

R3 10k

VG2 500.00m 0.00 3.25 Vin+ 500.00m -2.25 2.50 Vo 0.00 -2.50 0.00 5.00m 10.00m Time (s) 15.00m 20.00m

VG1

VG1 intended linear range signal Vp = 2.25V, f = 100Hz

V1 2.5 V+ V2 2.5 V-

C1 100n

C2 100n

VG1 + VG2 sum may activate ESD circuit on peaks

ESD cell paths may be activated during an EOS event

V2 5 L2 50n C2 1u +

*
D1 1N4148 D3 1N4148

L4 10n

D5 1N4148

Intended signal
VG1

T1 can become a near short between supplies!

Vout

Rs 1k

+ IOP1

D6 1N4148

D2 1N4148

Rs 1k

D4 1N4148

T1 !NPN RL 10k Rb 2k

VG2

Input EOS source

RF 10k

RI 1k

V1 5

* L1 50n

L3 10n C1 1u +

*may no longer represent a nearzero impedance at high frequencies

A supply clamp transistor failure during resulting from an input EOS/ESD event

One channel of RGB amplifier application

R1 500

R2 500 C2 10u V+ R3 75 + C1 10u + OP1 !OPAMP OUT

TL1

GRN OUT + GRN IN

R4 75

V+

VG1 R5 2k TERM T1 !NPN

Vcer clamp transistor

V+/V- wall-wart power supply without on/off switch

EOS-related CMOS operational-amplifier field failures

TI quad CMOS operational amplifier failing unexpectedly in air conditioner application TI FA report indicated the operational amplifier die had carbonized material on die and pin 4 (V+) to pin 11 (V-) short EOS analysis of the customer application input and output ESD circuits did not reveal any likely candidates

EOS-related CMOS operational-amplifier field failures

20 Vpk EOS on V+ line

A request for the Field Applications Engineers to observe and monitor the amplifier pins during the various operational cycles was made and provided
They found that a 20 Vpk pulse was appearing on the V+ line during operation of the air conditioner. The nominal supply voltage was +5 V The EOS was causing either the supply-to-supply ESD clamp to break down, or voltage breakdown of the amplifier transistor structures A higher voltage operational amplifier and a transient voltage suppressor on the V+ line were recommended

Input current limiting by external series-R

Where does the 10mA IOVERLOAD maximum originate?

Parasitic circuit latch testing

VS1 5 Compliance Range +/-7.5V I max 150mA VCCS1 + Pin under test +

A
+ +

AM1 U1 OPA348

+ VG1 -

I/O high I/O low

SW1 +

Ouput f loats during input pin tests

Input pins connected together VS2 0 during output pin tes t

Current injection latch test

The continuous input overload current is set to < 1/10th the JEDEC maximum latch test current (t 10ms)

Watch Vin during power up!

Iin excessively high while supply ramps

30.0m

AM115.0m 0.0 3.50 VG1 1.75 0.00 5.00 VG2 2.50 0.00 3.50 VM1 1.75 0.00 0 10m 20m Time (s) 30m 40m 50m

Instrumentation amplifier input protection

V+

Vin-

Ov er-Voltage Protection

IOP1 + R2 25k IOP3 R1 25k + R4 60k R6 60k Ref Vo R3 60k R5 60k

RG 25k EXT

Vin+

Ov er-Voltage Protection

+ IOP2

Vbias 0 Vbias
V-

+ IS1 10u Ib Comp 1n Vin+ T1 !NPN + -

A1
A3 +in A3 -in

A2 + Mirror of A1circuit

IOP2

C1 6p R1 25k RG 25k

Vd/2 1

+ +

Vcm 0

Vd/2 1

Ov er-Voltage Protection

Ext

VinT1 Noname T2 Noname D1 1N914

Excessive differential input over-voltage

Bipolar input operational amplifier
R1 500

Possible occurrences

T 10

When operating an operational amplifier as a comparator During slewing

U1 OPA227
-

V-

90%
Vo
+

8 VG1

Voltage (V)

VG1

Input-output voltage difference SR = 2.3V/us

R2 1k

V+

R3 1k

V1 15 V+ C1 100n

V2 15 VC2 100n
2

Vo

10%
0 0.0 1.0u 2.0u Time (s) 3.0u 4.0u 5.0u

Plot for illustrative purposes only!

OPA277 input-to-input differential over-voltage protection

modern bipolar op-amps have input clamps
R1 500 V2 15

Iin
20mA max
T28 !NPN

Gain stages and bias circuits

T23 !NPN

T41 !NPN

Vo

VinRL 1k

Pulse Vin+ Source

D3 1N914 D2 1N914 D1 1N914 D4 1N914 IS1 100u +

T44 !NPN

VG1

VG1 = 2VD + (Iin R1) + Vo

V1 15

If VO = 0V, then: Iin = (VG1 2VD) R1

Input overdrive of CMOS rail-to-rail IO chopper amplifiers

Back-to-back clamp diodes are inherent and internal to the chopper switch structures

When Vin exceeds a Vcm maximum Vo is forced to an output rail level The op-amp is forced outside of its linear operating range The feedback loop collapses and an input differential voltage develops One clamp diode or the other becomes forward biased and the input bias current can increase tremendously This may limit the use of this type of operational amplifier as a comparator

Overload Recovery
Auto-zero CMOS Operational-amplifiers
OPA335 Av = -50V/V
R1 2k R2 100k

Positive input +50mV 0mV 0V Negative output -2.5V

VG1

U1 OPA335 V+

Stepped from 50mV to 0mV

C1 100n

+ V1 2.5

VM1

Negative input 0mV

V2 2.5 C2 100n V-

-50mV 2.5V Positive output 0V

Vin Vs / Gain

Output inversion during input overdrive

U1 OPA234

+4.5V
Vin 5Vp-p + 2.0Vdc
-

VG1
+ +

+ VM1 -

-0.5V +4.5V VM1 0V

VG1 R1 50 V1 5 C1 10n

Output inversion

Supply pin over-voltage protection

L1 100u

Rs 5

LOAD
C1 1u RL 1k

VG1

+ -

VM1

5V Power supply

10.0

Smoothing a transient
with an RLC filter Transient amplitude effectively reduced Ringing dependent on RLC values and load R Amplifier PSRR becomes important
VG1 7.5

VG1

1us transient riding on 5V supply voltage

5.0 5.5

VM1
VM1 5.0

4.5 0 20u 40u Time (s) 60u 80u 100u

Supply pin over-voltage protection

Rs 10

LOAD
C1 10n RL 1k

VG1

+ -

VM1

5V Power supply Vz = 6.8V Z1 1N5342

T

10.0

Transient voltage suppression (TVS) diode 6.8V- 550V reverse standoff voltage Unidirectional & bidirectional models

VG1
VG1 7.5

5V 1us transient riding on +5V supply line

5.0 7.0

VM1
VM1 5.8

Ppk = 1.5kW (10 x 1000us) @ 25C

Cj 1nF @ 20V Littlefuse no. 1.5KE6.8, etc.

zener diode used in simulation no TVS model available

4.5 0 20u 40u Time (s) 60u 80u 100u

Supply pin over-voltage protection

Features Multilayer ceramic construction Operating voltage range VM(DC) = 5.5 to 120V Non-repetitive surge current (8/ 20us) Non-repetitive energy (10/ 1000us) response time <1ns for zinc oxide Inherent bidirectional clamping Wider temperature range and flatter response than solid-state TVS

Externally connected input protection devices

Transient voltage suppressors For CMOS, bipolar and SiGe Features: Available from 5.6 to 18V DC working voltage 18V AC working voltage 14V Turn-on-time <1ns
watch capacitance

Repetitive spike capability

uA J A pF

Externally connected input protection devices

Externally connected input protection devices

Schottky diodes provide enhanced input protection
SD1 BAS40 U1 OPA374
+ +

V1 5 C1 100n

SD2 BAS40 VG1 R1 5k

+ R2 5k -

VM1

Features: Forward voltage Forward current Leakage current * Diode capacitance VF 380mV, IF = 1mA IF = 200mA max (cont.) IR 100nA, VR = 30V Ctot 5pF, VR = 0V

* A small-signal silicon diode (IN4148) will likely turn on at lower voltage than the internal ESD silicon diode and may exhibit lower leakage current than a Schottky diode.

Externally connected input protection devices

An important point about added protection devices in the signal circuit

Protection components such as transient voltage suppressors (TVS), diodes and zener diodes all exhibit capacitance even when biased off The capacitance will vary to some extent with the voltage applied across the protection device Most often the capacitance does not have a linear capacitance to voltage relationship (voltage coefficient) This non-linear capacitance to voltage relationship may increase distortion in the protected circuit It will be most evident in a very low THD circuits, but may not degrade performance significantly

Power Line Communications (PLC) EOS environment IEC61000-4-5

Open-circuit surge pulse test 4kV, 1.2us tfront, 50us thalf-value

PLC EOS protection

Actual protection scheme will vary with application and layout

High voltage MOV and low-voltage TVS clamping

Fast rectifier and Schottky clamps

The internal output ESD cell is unlikely to withstand the open-circuit HV pulse - latching is probable

In Summary
EOS and ESD events may activate ESD protection but result in different outcomes Internal ESD circuits may sufficiently handle EOS Be aware of unique EOS situations such as power up and input slewing External EOS protection circuits will be required if device damage is likely to occur without it