ARM follows RISC Mechanism It is used for small size and high performance applications. Simple architecture low power consumption.
Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb instructions
32-bit Data Bus 32-bit Address Bus 37 32-bit registers 32-bit ARM instruction set 16-bit THUMB instruction set
32x8 Multiplier
Barrel Shifter
ARM Architecture
Typical RISC architecture:
Load/store architecture
Simple addressing modes Uniform and fixed-length instruction fields
Registers Description
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter 1 dedicated current program status register
User Mode
Banked Banked Bankedout out outRegisters Registers Registers Banked out Registers
User Abort
r8 r9 r10 r11 r12 r13 (sp) r14 r13 (lr) (sp) r14 (lr)
r7 r6 r8 r7 r9 r8 r10 r9 r11 r10 r12 r11 r13 r12 (sp) (sp) r13 r13 r14 (sp) (lr) r14 (lr) r14 r15 (lr) (pc) r15 (pc) cpsr spsr spsr cpsr
FIQ FIQ
r8 r9 r8 r10 r9 r11 r10 r12 r11 r13 r12 (sp) r14 r13 (lr) (sp) r14 (lr)
IRQ IRQ
SVC SVC
Undef Undef
Abort
spsr
spsr spsr
spsr spsr
spsr spsr
spsr spsr
spsr
Operating Modes
Seven operating modes:
User(Non Privileged mode)
Privileged:
exception modes
Undefined
Supervisor
10
IRQ : entered when a low priority (normal) interrupt is raised Supervisor : Entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations
FIQ
IRQ
SVC
Undef
Abort
r15 (pc)
cpsr spsr spsr spsr spsr spsr
Exceptions
Exception Reset Undefined instruction Software interrupt Mode Supervisor Undefined Supervisor Priority 1 6 6 IV Address 0x00000000 0x00000004 0x00000008
Abort
Abort IRQ FIQ
5
2 4 3
0x0000000C
0x00000010 0x00000018 0x0000001C
NZCVQ f
U n d e f i n e d s x
I F T mode c
J bit
Architecture 5TEJ only
Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits
Change to ARM state Change to exception mode Disable interrupts (if appropriate) Stores the return address in LR_<mode> Sets PC to vector address
Reset
Vector Table
Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices
Using a Barrel Shifter:The 2nd Register, optionally with shift operation Operand Shift value can be either be:
Operan d1 Operan d2
constant
Barrel Shifter
255.
ALU
Result
Pipeline Organization
3-stage pipeline: Fetch Decode - Execute Three-cycle latency,
Fetch
i+1
Decode Fetch
i+2
t+1
t+2
t+3
t+4
17
APB
UART Timer
AHB
Queries