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ABSTRACT:

Test generation problem for circuits is known to be NP-hard. Test patterns were generated using 2D-LFSR and faults were inserted in the netlist file generated using DFT . Calculating the fault coverage ,Test coverage, CPU timing.

LITERATURE SURVEY:ON TEST GENERATION WITH TEST VECTOR IMPROVEMENT .IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MARCH 2010. Irith P !"r#$%., F"&& ', IEEE, #$( S)(h#*#r M. R"((+, ,i-" F"&& ', IEEE.

Investigate the introduction of a new step, referred to as test vector improvement, into test generation processes.

After a fully specified test vector or a partially specified test cube is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies so as to increase the number of yet-undetected target faults that detects.

CONT
FORWARD-,OO.ING FAU,T SIMU,ATION FOR IMPROVED STATIC COMPACTION,/ IEEE TRANS. COMPUT.-AIDED DESIGN INTEGR.CIRCUITS SYST. OCT. 2001. I. POMERAN0 AND S. M. REDDY.

It is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size.

The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later.

CONT
OPMISR: The Foundation for Compressed ATPG Vectors. ITC INTERNATIONAL TEST CONFERENCE .2001 IEEE. C#r& 1#r$h#rt, V#$"22# 1r)$*h r2t, Fr#$* Di2t&"r, O'"$ F#r$2' rth, 1ri $ ."&&"r/, 1"r$( . ".

Rapid increases in the wire-able gate counts of ASI s stresses e!isting manufacturing test e"uipment in terms of test data volume and test capacity.

shows compression efficiencie allowing a more than #$!-fold reduction in tester scan buffer data volume on AT%& compacted tests into '! folded shares.

PROPOSED WORK
Combining Design vision and Tetramax (synopsys). Generate the test pattern for sequential and combinational circuits. Calculating the fault and test coverage along with CPU timing excluding routing area. Compare the results with some of the IEEE papers using ISCAS 89 Benchmark circuts.

TOOLS REQUIRED:Tetra max. Design vision. Xilinx. Coding used : Verilog ISCAS 89 Sequential circuits.

Work done
Generating the netlist for ISCAS 89 benchmark circuits. Converting the circuits into scan able form. Finding the area and power used for benchmark circuits before and after scan using design vision. Inserting the faults in the circuits and generating test pattren ,fault coverage and test coverage for different faults .

AREA CALCULATION

POWERCALCULATION

Fault & test coverage for uncollapsed struck at fault

Fault & test coverage for collapsed struck at fault

Fault & test coverage for uncollapsed iddq fault

Fault & test coverage for uncollapsed iddq fault

Transition faults

Comparison results for s-a-f

Comparison results of transition faults

S27 benchmark circuit

// // // // // // // // // // // // // // // // // // //

Uncollapsed Stuck Fault Summary Report ----------------------------------------------fault class code #faults ------------------------------ ---- --------Detected DT 94 Possibly detected PT Undetectable UD ! "TP# untestable "U ! $ot detected $D ! ----------------------------------------------total faults %!& test co'era(e 9)*! + ----------------------------------------------Pattern Summary Report ----------------------------------------------#internal patterns %% #full,se-uential patterns %% -----------------------------------------------

Patterns generated
1.pattern = 0; // 0 #0 PI = 7'b0111001; 2.pattern = 1; // 400 #0 PI = 7'b0001010; 3.pattern = 2; // 800 #0 PI = 7'b0010011; 4.pattern = 3; // 2000 #0 PI = 7'b0100111; 5.pattern = 4; // 2800 #0 PI = 7'b0010110; 6.pattern = 5; // 3200 #0 PI = 7'b0001100; 7.pattern = 6; // 3600 #0 PI = 7'b0110000; 8.pattern = 7; // 4400 #0 PI = 7'b0001010; 9.pattern = 8; // 4800 #0 PI = 7'b0001110; 10.pattern = 9; // 5600 #0 PI = 7'b0101010 11.pattern = 10; // 7000 #0 PI = 7'b0001110;

SCHEMATIC VIEW

LFSR ALGORITHM

Linear feedback shift registers make extremely good pseudorandom pattern generators. Generated patterns were given to the input of the iscas 89 benchmark circuits .

Fault free and Faulty CUT were observed by inserting the faults.
FAULT FREE CIRCUIT

FAULTY OUTPUT

REFERENCE
1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Testing for singlestuck faults, in Digital Systems Testing and Testable Design. Piscataway,NJ: I 2.I. Pomeranz and S. M. Reddy, Forward-looking fault simulation forimproved static compaction, IEEE Trans. Comput.-Aided Design Integr.Circuits Syst., vol. 20, no. 10, pp. 1262 1265, Oct. 2001.EEE Press, 1995, pp. 181281. 3. I. Pomeranz and S. M. Reddy, Forming N-detection test sets without test generation, Assoc. Comput. Machinery Trans. Design Autom. Electron. Syst., vol. 12, no. 2, pp. 118, 2007. 4. S. Kajihara, I. Pomeranz, K. Kinoshita, and S. M. Reddy, Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits, IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 14, no. 12, pp. 14961504, Dec. 1995. 5. F. Corno, P. Prinetto, M. Rebaudengo, and M. S. Reorda, GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 8, pp. 9911000, Aug. 1996. 6. K.-H. Tsai, J. Rajski, and M. Marek-Sadowska, Scan encoded testpattern generation for BIST, in Proc. Int. Test Conf., 1997, pp. 548556. 7. J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H.Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian,Embedded deterministic test for low cost manufacturing test, in Proc. Int. Test Conf., 2002, pp. 301310.

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