1

Data Converters Sample-and-Hold Professor Y. Chiu

EECT 7327 Fall 2012
Sample-and-Hold (S/H) Basics
ZOH vs. Track-and-Hold (T/H)
2
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Zero acquisition time
Infinite bandwidth
Not realistic
T/2 acquisition time
Finite bandwidth
Practical
V(t)
t
0 T 2T
T
V(t)
t
0
T/2
T 2T
H T H T H T H T H T
A Simple T/H (Top-Plate Sampling)
3
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V
o

C
S
R
S
V
i
MOS technology is naturally suitable for implementing T/H
The lowpass SC network determines the tracking bandwidth
Non-idealities: signal-dependent R
on
, charge injection, aperture, etc.
R
on
0 V
DD
V
i
V
Tn
V
Tp
PMOS
NMOS
CMOS
( )
i th DD ox
1
on
V V V
L
W
C R =

Tracking Bandwidth (TBW)

4
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
R
on
C
S
V
i
V
o
R
S
R
on
0 V
DD
V
i
( )
S on S
C R R 1 TBW + =
Tracking bandwidth determines how promptly V
o
can follow V
i

Typically TBW is many times greater than the max signal bandwidth
Whats wrong with the concept of linear filtering if R
on
is constant?
Dispersion
5
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
( )
( )
( ) ( ) | | j H
d
d
t
: delay Group

j H
t
: delay Phase
g
p
Z =
Z
=
Magnitude response
Non-uniform phase delay
Non-uniform group delay
|H(j)|
1
0
ZH(j)
-45
0
-90

0

0
Dispersion
6
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Waveform is not very sensitive to the lowpass magnitude response as long
as the signal bandwidth is on the order of TBW
Waveform distortion is mainly due to non-uniform phase and group delays
R
on
C
S
V
i
V
o
R
S
t t
Signal-Dependent R
on

7
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V
o

C
S
R
S
V
i
Signal-dependent R
on
signal-dependent TBW extra waveform
distortion
Neither signal-dependent R
on
nor dispersion is of concern if TBW is
sufficiently large (>> f
in
, depending on the target accuracy)
R
on
0 V
DD
V
i
V
Tn
V
Tp
PMOS
NMOS
CMOS
( )
i th DD ox
1
on
V V V
L
W
C R =

Ideal T/H
8
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Sufficient tracking bandwidth negligible tracking error
Well-defined sampling instant (asserted by clock rising/falling edge)
Zero track-mode and hold-mode offset errors
V(t)
t
Track Hold Hold
T/H Errors (Track Mode)
9
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Finite tracking bandwidth tracking error, T/H memory
Track-mode offset, gain error, and nonlinearity
V(t)
t

2
Droop
Track Hold Hold
t
Acquisition Time (t
acq
)
10
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
R
on
C
S
V
i
V
o
R
S
( )
S on S
C R R
TBW
1
+ = =
Short L, thin t
ox
, large W, large V
ov
, and small V
i
help reduce R
on

Accuracy t
acq
1% (7b) 5t
0.1% (10b) 7t
0.01% (13b) 9t
( )
( )
ch
2
i th DD ox
2
i th DD ox
on
Q
L
V V V WL C
L
V V V
L
W
C
1
R =

=

=
T/H Errors (T-to-H Transition)
11
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Pedestal error (often signal-dependent) resulted from switch turn-off
nonidealities (clock feedthrough and charge injection)
Aperture delay the delay t b/t hold command and hold action
Aperture jitter the random variation in t (i.e., sampling clock jitter)
V(t)
t

2
Droop
Track Hold Hold
t
Switch Non-Idealities
12
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012

V
DD
0
V
in
+V
th
Switch on Switch off
V
out

C
S
Z
i
V
in
C
gd
C
gs
Q
ch
Clock feedthrough (CF) Charge injection (CI)
Fast turn-off
Slow turn-off
DD
S gs
gs
V
C C
C
V
+
=
( )
( )
S gs
in th DD ox
C C 2
V V V WL C
V
+

=
( )
th in
S gs
gs
V V
C C
C
V +
+
=
0 V =
Pedestal Error of Top-Plate T/H
13
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
( )
( )
= + +
| | (
= + +
| (
|
+ + +
(
\ .
o i os
gs
ox ox
o i DD DD th
gs S gs S gs S
V 1 V V
C
C WL C WL 1 1
V 1 V V V V
2 C C C C 2 C C
( )
= + +
| |
=
|
|
+ +
\ .
o i os
gs gs
o i th
gs S gs S
V 1 V V
C C
V 1 V V
C C C C
Slow turn-off:
Fast turn-off:
Watch out for nonlinear errors!
Speed-Accuracy Tradeoff of T/H
14
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
S
ch
C
Q
2
1
V ~
Pedestal error:
TBW:
S
2
ch
S on
C L
Q
C R
1
TBW = ~
2
L
Q
C L
C
Q
2
1
TBW
V
2
ch
S
2
S
ch
= ~
Therefore:
Technology scaling improves T/H performance!
Aperture Delay (t)
15
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Fixed aperture delay is usually not of problem in a single-path T/H
Non-uniform aperture delays among time-interleaved T/H paths cause
significant errors (t
1
, t
2
are also called sampling clock skew)
CH 1
CH 2

2
V
in

2
Aperture Jitter
16
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V(t)
t
V
Track Hold
t
dV
dt
Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, Jitter analysis of high-speed
sampling systems, IEEE Journal of Solid-State Circuits, vol. 25, issue 1, pp. 220-
224, 1990.
Aperture Jitter
17
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
( ) ( ) ( ) ( )
( ) ( ) | |
2
A
t
2
A
dt t cos A
T
1
t t
onary" Cyclostati " t Acos t t Asin t V t
2
t
2 2
2
2 2
T
0
2
2 2
i
= = =
~ =
}
( ) ( )
( ) ( ) ( ) ( )
( ) ( )
( ) ( )
= + (

= +
(
| | | | | |
= +
| | | (
\ . \ . \ .

~ +
i
2
V t Asin t t
Asin t cos t Acos t sin t
t t t
Asin t 1 sin Acos t 2sin cos
2 2 2
Asin t t Acos t for small t
2
t
2
2
t
2 2 2

1
2
A
2
A
SNR =
|
|
.
|

\
|
=

Aperture Jitter
18
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
10
6
10
7
10
8
10
9
0
20
40
60
80
100
120
140
Input Freq [Hz]
S
N
R

[
d
B
]
o
t
= 0.1ps
o
t
= 1ps
o
t
= 10ps
o
t
= 100ps
( )
t 10
LOG 20 SNR =
T/H Errors (Hold Mode)
19
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Hold-mode droop caused by off-switch/diode/gate leakage
Hold-mode input feedthrough (i.e., due to capacitive coupling)
V(t)
t

2
Droop
Track Hold Hold
t
Evaluating T/H Performance
20
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
kT/C noise:
SNDR:
2

2
2 2
2
N
2
i
V t
2
A
V
V
SNDR
+ +
=
S
0
2
S
2
N
C
kT
df
RC f j2 1
1
4kTR V =
+
=
}

Noise Distortion
C
S
kT/C
100pF 6.4V
1pF 64V
10fF 640V
T = 300K
Jitter
21
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
MOS S/H Techniques
Simple Top-Plate Sampling
22
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V
o

C
S
R
S
V
i
Pros
Simple, minimum number of devices
Potentially wideband, zero track-mode offset
Cons
Signal-dependent tracking bandwidth
Signal-dependent charge injection and clock feedthrough
Signal-dependent aperture delay (sampling point)
Signal-Dependent Aperture Delay
23
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Non-uniform sampling due to signal-dependent aperture delay causes
distortion in top-plate S/H
Sharp clock edge and small V
in
mitigate the delay variation

V
DD
0
V
i
+V
th
(V
i
)
Switch on Switch off
V
th
(V
i
)
( ) ( )
( )
( )
=
(
| |
=
( |
(
\ .

i
i
o
V t Asin t
V t
V t Asin t
SR
Signal Distortion
24
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
( ) ( ) ( ) ( )
( )
( )
( ) ( ) t 2 sin A
2
1
SR

t Acos
SR
t Asin
t
t Acos
SR
V
t V t V t
2
i
o i
= ~
~ =
( )
( ) ( )
( ) ( )
(
| |
=
| (
\ .

| | | |
=
| |
\ . \ .
~
i
o
i i
i i
V
V t Asin t
SR
V V
Asin t cos Acos t sin
SR SR
V V
Asin t Acos t for small
SR SR
2 2
2
2
2
2
A
SR 4
2
SR 2
A
2
A
SDR

=
|
|
.
|

\
|

=

2
nd
-order
CMOS Switch
25
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
R
on
still depends on V
in
and is sensitive to N/P mismatch
Large parasitic cap due to PMOS switch for symmetric R
on
Clock rising/falling edge alignment
R
on
0 V
DD
V
i
V
Tn
V
Tp
PMOS
NMOS
CMOS
V
o
C
S
V
i

Clock Bootstrapping
26
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Constant gate overdrive voltage V
GS
= V
DD
for the switch
R
on
is not dependent on V
in
to the first order (body effect?)
NMOS device only with less parasitic capacitance
R
on
0 V
DD
V
i
Out In
M
1
V
DD

Clock Bootstrapping
27
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Out
M
6
C C
2
C
1
M
5

In
M
4
M
3
M
2
M
1
V
DD
V
SS

Ref: A. M. Abo and P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC,
IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp. 599-606, 1999.
Clock Bootstrapping (=0)
28
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Out
C

In
M
2
M
1

V
DD
V
SS
Out
C

In
M
3
M
1
M
2

Clock Bootstrapping (=1)

29
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Out
C

In
M
3
M
1
M
2

Out
C

In
M
2
M
1

V
DD
V
SS
Dummy Switch
30
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Initial size of dummy chosen with the assumption of a 50/50 split of
Q
ch
; usually (W/L)
dummy
< (W/L)
switch
in practice
The nonlinear dependence of CI on Z
i
, C
S
, and clock rise/fall time
makes it difficult to achieve a precise cancellation
_ rising edge must trail falling edge
V
o

W
L C
S
W
2L

V
i
Balanced Switch + Dummy
31
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V
o

W
L C
S
W
2L

V
i
C
S
Ref: L. A. Bienstman and H. J. De Man, An eight-channel 8 bit microprocessor
compatible NMOS D/A converter with programmable scaling, IEEE Journal of Solid-
State Circuits, vol. 15, issue 6, pp. 1051-1059, 1980.
TBW
Parasitics
Fully-Differential T/H
32
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
All even-order distortions cancelled, including the signal-dependent
aperture delay-induced distortion
Actual cancellation limited by P/N mismatch (1-10% typically)
f
in
0.5GHz
V
DD
1.8V
t
f
0.1ns
A (V
in
) 0.5V
SDR (SE) 20-30 dB
SDR (DF) 40-50 dB
V
o
+
C
S
+
V
i
+
V
o
-
C
S
-
V
i
-

M
1
M
2
E.g.
Bottom-Plate Sampling
33
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
AC-ground switch opens slightly earlier than input switches
Signal-independent CF and CI of switch
e
to the first order!
Top-plate switch can be further bootstrapped
Typically for applications of more than 8-bit resolution

Less tracking bandwidth due to more switches in series
Signal swing at node X is not entirely zero!

C
S
V
i

e
X
34
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Sample-and-Hold Amplifier
(SHA)
Inverting SHA
35
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
V
i
+
V
o
+
V
o
-
V
i
-
C
S
+

2
C
S
-

1e

2
C
H
+
C
H
-

1
Inverting, closed-loop gain determined by the ratio C
S
/C
H

CMOS or bootstrapped switches are required when passing signals
with large swing (where?)

1e

2
T H
Inverting SHA (Track-Mode)
36
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
CF and CI are independent of V
in
and cancelled differentially

1e
switch is equivalent to two switches of half channel length
faster, less CF and CI
V
i
+
V
i
-
C
S
+
C
S
-

1e

1
C
H
+
C
H
-

1
W
L

1e

1e
W
L/2
W
L/2
Inverting SHA (Hold-Mode)
37
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
For 1X gain (C
S
= C
H
), the feedback factor is about 1/2
Floating switch
2
in hold-mode flexible input common mode
Useful for single-ended to differential conversion
V
o
+
V
o
-
C
S
+

2
C
S
-

2
C
H
+
C
H
-
CM?
DM?
Differential Mode
38
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
DM charge transfer is complete
V
o
+
V
o
-
C
S
+

2
C
S
-

2
C
H
+
C
H
-
DM half circuit
V
o
+
C
S

2
A
dm
C
H
V
i,dm

2

Common Mode
39
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
CM charge is not transferred!
V
o
+
V
o
-
C
S
+

2
C
S
-

2
C
H
+
C
H
-
CM half circuit

V
o
+
C
S

2
A
cm
C
H
V
i,cm
Flip-Around SHA
40
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2012
Non-inverting, 1X closed-loop gain
Close-to-unity feedback factor in hold mode
CF/CI independent of V
in
and cancelled differentially
V
i
+
V
o
+
V
o
-
V
i
-
C
S
+

1e
C
S
-

1e

1e

2
T H