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Chapter 4 - ISA

1.The Von Neumann Model

The Stored Program Computer


1943: ENIAC
Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?) Hard-wired program -- settings of dials and switches.

1944: Beginnings of EDVAC


among other improvements, includes program stored in memory

1945: John von Neumann


wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC

The basic structure proposed in the draft became known as the von Neumann machine (or model).
a memory, containing instructions and data a processing unit, for performing arithmetic and logical operations a control unit, for interpreting instructions
For more history, see http://www.maxmon.com/history.htm http://www.webmienphi.com/mydocuments/TH2.aspx

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Von Neumann Model


MEMORY
MAR MDR

INPUT
Keyboard Mouse Scanner Disk

OUTPUT PROCESSING UNIT


ALU TEMP
Monitor Printer LED Disk

CONTROL UNIT
PC IR

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Memory
2k x m array of stored bits Address
unique (k-bit) identifier of location

Contents
m-bit value stored in location

0000 0001 0010 0011 0100 0101 0110 1101 1110 1111

00101101

Basic Operations: LOAD


read a value from a memory location


10100010

STORE
write a value to a memory location

4-4

Interface to Memory
How does processing unit get data to/from memory? MAR: Memory Address Register MEMORY MDR: Memory Data Register

MAR
To LOAD a location (A):
1. Write the address (A) into the MAR. 2. Send a read signal to the memory. 3. Read the data from MDR.

MDR

To STORE a value (X) to a location (A):


1. Write the data (X) to the MDR. 2. Write the address (A) into the MAR. 3. Send a write signal to the memory.

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Processing Unit
Functional Units
ALU = Arithmetic and Logic Unit could have many functional units. some of them special-purpose (multiply, square root, ) LC-3 performs ADD, AND, NOT

PROCESSING UNIT
ALU TEMP

Registers
Small, temporary storage Operands and results of functional units LC-3 has eight registers (R0, , R7), each 16 bits wide

Word Size
number of bits normally processed by ALU in one instruction also width of registers LC-3 is 16 bits

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Input and Output


Devices for getting data into and out of computer memory
INPUT OUTPUT
Monitor Printer LED Disk

Each device has its own interface, usually a set of registers like the memorys MAR and MDR

Keyboard Mouse Scanner Disk

LC-3 supports keyboard (input) and monitor (output) keyboard: data register (KBDR) and status register (KBSR) monitor: data register (DDR) and status register (DSR)

Some devices provide both input and output


disk, network

Program that controls access to a device is usually called a driver.


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Control Unit
Orchestrates execution of the program
CONTROL UNIT
PC IR

Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit:
reads an instruction from memory
the instructions address is in the PC

interprets the instruction, generating signals that tell the other components what to do
an instruction may take many machine cycles to complete

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Instruction Processing
Fetch instruction from memory Decode instruction

Evaluate address
Fetch operands from memory

Execute operation
Store result
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Instruction
The instruction is the fundamental unit of work. Specifies two things:
opcode: operation to be performed operands: data/locations to be used for operation

An instruction is encoded as a sequence of bits. (Just like data!) Often, but not always, instructions have a fixed length, such as 16 or 32 bits. Control unit interprets instruction: generates sequence of control signals to carry out operation. Operation is either executed completely, or not at all. A computers instructions and their formats is known as its Instruction Set Architecture (ISA).

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Example: LC-3 ADD Instruction


LC-3 has 16-bit instructions.
Each instruction has a four-bit opcode, bits [15:12].

LC-3 has eight registers (R0-R7) for temporary storage.


Sources and destination of ADD are registers.

Add the contents of R2 to the contents of R6, and store the result in R6.
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Example: LC-3 LDR Instruction


Load instruction -- reads data from memory Base + offset mode:
add offset to base register -- result is memory address load from memory address into destination register

Add the value 6 to the contents of R3 to form a memory address. Load the contents of that memory location to R2.
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Instruction Processing: FETCH


Load next instruction (at address stored in PC) from memory into Instruction Register (IR).
Copy contents of PC into MAR. Send read signal to memory. Copy contents of MDR into IR.

F D EA OP

Then increment PC, so that it points to the next instruction in sequence.


PC becomes PC+1.

EX
S
4-13

Instruction Processing: DECODE


First identify the opcode.
In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode.

F D EA OP

Depending on opcode, identify other operands from the remaining bits.


Example: for LDR, last six bits is offset for ADD, last three bits is source operand #2

EX
S
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Instruction Processing: EVALUATE ADDRESS


For instructions that require memory access, compute address used for access. Examples:
add offset to base register (as in LDR) add offset to PC add offset to zero

F D EA OP

EX
S
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Instruction Processing: FETCH OPERANDS


Obtain source operands needed to perform operation. Examples:
load data from memory (LDR) read data from register file (ADD)

F D EA OP

EX
S
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Instruction Processing: EXECUTE


Perform the operation, using the source operands. Examples:
send operands to ALU and assert ADD signal do nothing (e.g., for loads and stores)

F D EA OP

EX
S
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Instruction Processing: STORE RESULT


Write results to destination. (register or memory) Examples:
result of ADD is placed in destination register result of memory load is placed in destination register for store instruction, data is stored to memory write address to MAR, data to MDR assert WRITE signal to memory

F D EA OP

EX
S
4-18

Changing the Sequence of Instructions


In the FETCH phase, we increment the Program Counter by 1. What if we dont want to always execute the instruction that follows this one?
examples: loop, if-then, function call

Need special instructions that change the contents of the PC. These are called control instructions.
jumps are unconditional -- they always change the PC branches are conditional -- they change the PC only if some condition is true (e.g., the result of an ADD is zero)

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Example: LC-3 JMP Instruction


Set the PC to the value contained in a register. This becomes the address of the next instruction to fetch.

Load the contents of R3 into the PC.

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Instruction Processing Summary


Instructions look just like data -- its all interpretation.

Three basic kinds of instructions:


computational instructions (ADD, AND, ) data movement instructions (LD, ST, ) control instructions (JMP, BRnz, )

Six basic phases of instruction processing:

F D EA OP EX S
not all phases are needed by every instruction
phases may take variable number of machine cycles

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Control Unit State Diagram


The control unit is a state machine. Here is part of a simplified state diagram for the LC-3:

A more complete state diagram is in Appendix C. It will be more understandable after Chapter 5.

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2. The LC-3

Instruction Set Architecture


ISA = All of the programmer-visible components and operations of the computer
memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes

ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 4-24

LC-3 Overview: Memory and Registers


Memory
address space: 216 locations (16-bit addresses) addressability: 16 bits

Registers
temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each 16 bits wide how many bits to uniquely identify a register? other registers not directly addressable, but used by (and affected by) instructions PC (program counter), condition codes

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LC-3 Overview: Instruction Set


Opcodes
15 opcodes Operate instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP some opcodes set/clear condition codes, based on result: N = negative, Z = zero, P = positive (> 0)

Data Types
16-bit 2s complement integer

Addressing Modes
How is the location of an operand specified? non-memory addresses: immediate, register memory addresses: PC-relative, indirect, base+offset 4-26

Operate Instructions
Only three operations: ADD, AND, NOT

Source and destination operands are registers


These instructions do not reference memory. ADD and AND can use immediate mode, where one operand is hard-wired into the instruction.

Will show dataflow diagram with each instruction.


illustrates when and where data moves to accomplish the desired operation

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NOT (Register)

Note: Src and Dst could be the same register.

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ADD/AND (Register)

this zero means register mode

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ADD/AND (Immediate)

this one means immediate mode

Note: Immediate field is sign-extended.

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Using Operate Instructions


With only ADD, AND, NOT
How do we subtract?

How do we OR?

How do we copy from one register to another?

How do we initialize a register to zero?

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Data Movement Instructions


Load -- read data from memory to register
LD: PC-relative mode LDR: base+offset mode LDI: indirect mode

Store -- write data from register to memory


ST: PC-relative mode STR: base+offset mode STI: indirect mode

Load effective address -- compute address, save in register


LEA: immediate mode does not access memory

4-32

PC-Relative Addressing Mode


Want to specify address directly in the instruction
But an address is 16 bits, and so is an instruction! After subtracting 4 bits for opcode and 3 bits for register, we have 9 bits available for address.

Solution:
Use the 9 bits as a signed offset from the current PC.

9 bits: 256 offset 255 Can form any address X, such that: PC 256 X PC 255
Remember that PC is incremented as part of the FETCH phase; This is done before the EVALUATE ADDRESS stage.

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LD (PC-Relative)

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ST (PC-Relative)

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Indirect Addressing Mode


With PC-relative mode, can only address data within 256 words of the instruction.
What about the rest of memory?

Solution #1:
Read address from memory location, then load/store to that address.

First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store.

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LDI (Indirect)

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STI (Indirect)

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Base + Offset Addressing Mode


With PC-relative mode, can only address data within 256 words of the instruction.
What about the rest of memory?

Solution #2:
Use a register to generate a full 16-bit address.

4 bits for opcode, 3 for src/dest register, 3 bits for base register -- remaining 6 bits are used as a signed offset.
Offset is sign-extended before adding to base register.

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LDR (Base+Offset)

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STR (Base+Offset)

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Load Effective Address


Computes address like PC-relative (PC plus signed offset) and stores the result into a register. Note: The address is stored in the register, not the contents of the memory location.

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LEA (Immediate)

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Example
Address Instruction Comments
R1 PC 3 = x30F4 R2 R1 + 14 = x3102 M[PC - 5] R2 M[x30F4] x3102

x30F6 x30F7 x30F8

1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1

x30F9
x30FA x30FB x30FC

0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0
0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1
opcode

R2 0
R2 R2 + 5 = 5 M[R1+14] R2 M[x3102] 5 R3 M[M[x30F4]] R3 M[x3102] R3 5

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Control Instructions
Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch
branch is taken if a specified condition is true signed offset is added to PC to yield new PC else, the branch is not taken PC is not changed, points to the next sequential instruction

Unconditional Branch (or Jump)


always changes the PC

TRAP
changes PC to the address of an OS service routine routine will return control to the next instruction (after TRAP)

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Condition Codes
LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times
Based on the last instruction that altered a register

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Branch Instruction
Branch specifies one or more condition codes. If the set bit is specified, the branch is taken.
PC-relative addressing: target address is made by adding signed offset (IR[8:0]) to current PC.
Note: PC has already been incremented by FETCH stage.

Note: Target must be within 256 words of BR instruction.

If the branch is not taken, the next sequential instruction is executed.

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BR (PC-Relative)

What happens if bits [11:9] are all zero? All one?

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Using Branch Instructions


Compute sum of 12 integers.
Numbers start at location x3100. Program starts at location x3000.

R1 x3100 R3 0 R2 12

R2=0?

NO

R4 M[R1] R3 R3+R4 R1 R1+1 R2 R2-1

YES

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Sample Program
Address Instruction Comments
R1 x3100 (PC+0xFF) R3 0 R2 0 R2 12 If Z, goto x300A (PC+5) Load next value to R4 Add to R3 Increment R1 (pointer)

x3000 x3001 x3002 x3003 x3004 x3005 x3006 x3007

1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1

X3008
x3009

0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0

Decrement R2 (counter)
Goto x3004 (PC-6)

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JMP (Register)
Jump is an unconditional branch -- always taken.
Target address is the contents of a register. Allows any target address.

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TRAP

Calls a service routine, identified by 8-bit trap vector.


vector routine x23 x21 x25 input a character from the keyboard output a character to the monitor halt the program

When routine is done, PC is set to the instruction following TRAP.


(Well talk about how this works later.)

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Another Example
Count the occurrences of a character in a file
Program begins at location x3000 Read character from keyboard Load each character from a file
File is a sequence of memory locations Starting address of file is stored in the memory location immediately after the program

If file character equals input character, increment counter End of file is indicated by a special ASCII value: EOT (x04) At the end, print the number of characters and halt
(assume there will be less than 10 occurrences of the character)

A special character used to indicate the end of a sequence is often called a sentinel.
Useful when you dont know ahead of time how many times to execute a loop.

4-53

Flow Chart
Count = 0
(R2 = 0)

Done?
(R1 ?= EOT)

YES

Convert count to ASCII character


(R0 = x30, R0 = R2 + R0)

Ptr = 1st file character


(R3 = M[x3012]) YES

NO

Print count Match?


(R1 ?= R0) NO (TRAP x21)

Input char from keybd


(TRAP x23)

HALT Incr Count Load char from file


(R1 = M[R3]) (R2 = R2 + 1) (TRAP x25)

Load next char from file


(R3 = R3 + 1, R1 = M[R3])

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Program (1 of 2)
Address Instruction Comments
R2 0 (counter) R3 M[x3012] (ptr) Input to R0 (TRAP x23) R1 M[R3] R4 R1 4 (EOT) If Z, goto x300E R1 NOT R1 R1 R1 + 1

x3000 x3001 x3002 x3003 x3004 x3005 x3006 x3007

0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1

X3008
x3009

0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1

R1 R1 + R0
If N or P, goto x300B

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Program (2 of 2)
Address Instruction Comments
R2 R2 + 1 R3 R3 + 1 R1 M[R3] Goto x3004 R0 M[x3013] R0 R0 + R2 Print R0 (TRAP x21) HALT (TRAP x25)

x300A x300B x300C x300D x300E x300F x3010 x3011

0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1

X3012
x3013

Starting Address of File


0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
ASCII x30 (0)

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LC-3 Data Path Revisited

Filled arrow = info to be processed. Unfilled arrow = control signal.

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Data Path Components


Global bus
special set of wires that carry a 16-bit signal to many components inputs to the bus are tri-state devices, that only place a signal on the bus when they are enabled only one (16-bit) signal should be enabled at any time control unit decides which signal drives the bus any number of components can read the bus register only captures bus data if it is write-enabled by the control unit

Memory
Control and data registers for memory and I/O devices memory: MAR, MDR (also control signal for read/write)

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Data Path Components


ALU
Accepts inputs from register file and from sign-extended bits from IR (immediate field). Output goes to bus. used by condition code logic, register file, memory

Register File
Two read addresses (SR1, SR2), one write address (DR) Input from bus result of ALU operation or memory read Two 16-bit outputs used by ALU, PC, memory address data for store instructions passes through ALU

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Data Path Components


PC and PCMUX
Three inputs to PC, controlled by PCMUX 1. PC+1 FETCH stage 2. Address adder BR, JMP 3. bus TRAP (discussed later)

MAR and MARMUX


Two inputs to MAR, controlled by MARMUX 1. Address adder LD/ST, LDR/STR 2. Zero-extended IR[7:0] -- TRAP (discussed later)

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Data Path Components


Condition Code Logic
Looks at value on bus and generates N, Z, P signals Registers set only when control unit enables them (LD.CC) only certain instructions set the codes (ADD, AND, NOT, LD, LDI, LDR, LEA)

Control Unit Finite State Machine


On each machine cycle, changes control signals for next phase of instruction processing who drives the bus? (GatePC, GateALU, ) which registers are write enabled? (LD.IR, LD.REG, ) which operation should ALU perform? (ALUK) Logic includes decoder for opcode, etc. 4-61