The basic structure proposed in the draft became known as the von Neumann machine (or model).
a memory, containing instructions and data a processing unit, for performing arithmetic and logical operations a control unit, for interpreting instructions
For more history, see http://www.maxmon.com/history.htm http://www.webmienphi.com/mydocuments/TH2.aspx
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INPUT
Keyboard Mouse Scanner Disk
CONTROL UNIT
PC IR
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Memory
2k x m array of stored bits Address
unique (k-bit) identifier of location
Contents
m-bit value stored in location
0000 0001 0010 0011 0100 0101 0110 1101 1110 1111
00101101
10100010
STORE
write a value to a memory location
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Interface to Memory
How does processing unit get data to/from memory? MAR: Memory Address Register MEMORY MDR: Memory Data Register
MAR
To LOAD a location (A):
1. Write the address (A) into the MAR. 2. Send a read signal to the memory. 3. Read the data from MDR.
MDR
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Processing Unit
Functional Units
ALU = Arithmetic and Logic Unit could have many functional units. some of them special-purpose (multiply, square root, ) LC-3 performs ADD, AND, NOT
PROCESSING UNIT
ALU TEMP
Registers
Small, temporary storage Operands and results of functional units LC-3 has eight registers (R0, , R7), each 16 bits wide
Word Size
number of bits normally processed by ALU in one instruction also width of registers LC-3 is 16 bits
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Each device has its own interface, usually a set of registers like the memorys MAR and MDR
LC-3 supports keyboard (input) and monitor (output) keyboard: data register (KBDR) and status register (KBSR) monitor: data register (DDR) and status register (DSR)
Control Unit
Orchestrates execution of the program
CONTROL UNIT
PC IR
Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit:
reads an instruction from memory
the instructions address is in the PC
interprets the instruction, generating signals that tell the other components what to do
an instruction may take many machine cycles to complete
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Instruction Processing
Fetch instruction from memory Decode instruction
Evaluate address
Fetch operands from memory
Execute operation
Store result
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Instruction
The instruction is the fundamental unit of work. Specifies two things:
opcode: operation to be performed operands: data/locations to be used for operation
An instruction is encoded as a sequence of bits. (Just like data!) Often, but not always, instructions have a fixed length, such as 16 or 32 bits. Control unit interprets instruction: generates sequence of control signals to carry out operation. Operation is either executed completely, or not at all. A computers instructions and their formats is known as its Instruction Set Architecture (ISA).
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Add the contents of R2 to the contents of R6, and store the result in R6.
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Add the value 6 to the contents of R3 to form a memory address. Load the contents of that memory location to R2.
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F D EA OP
EX
S
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F D EA OP
EX
S
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F D EA OP
EX
S
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F D EA OP
EX
S
4-16
F D EA OP
EX
S
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F D EA OP
EX
S
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Need special instructions that change the contents of the PC. These are called control instructions.
jumps are unconditional -- they always change the PC branches are conditional -- they change the PC only if some condition is true (e.g., the result of an ADD is zero)
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F D EA OP EX S
not all phases are needed by every instruction
phases may take variable number of machine cycles
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A more complete state diagram is in Appendix C. It will be more understandable after Chapter 5.
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2. The LC-3
ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 4-24
Registers
temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each 16 bits wide how many bits to uniquely identify a register? other registers not directly addressable, but used by (and affected by) instructions PC (program counter), condition codes
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Data Types
16-bit 2s complement integer
Addressing Modes
How is the location of an operand specified? non-memory addresses: immediate, register memory addresses: PC-relative, indirect, base+offset 4-26
Operate Instructions
Only three operations: ADD, AND, NOT
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NOT (Register)
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ADD/AND (Register)
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ADD/AND (Immediate)
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How do we OR?
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Solution:
Use the 9 bits as a signed offset from the current PC.
9 bits: 256 offset 255 Can form any address X, such that: PC 256 X PC 255
Remember that PC is incremented as part of the FETCH phase; This is done before the EVALUATE ADDRESS stage.
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LD (PC-Relative)
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ST (PC-Relative)
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Solution #1:
Read address from memory location, then load/store to that address.
First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store.
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LDI (Indirect)
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STI (Indirect)
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Solution #2:
Use a register to generate a full 16-bit address.
4 bits for opcode, 3 for src/dest register, 3 bits for base register -- remaining 6 bits are used as a signed offset.
Offset is sign-extended before adding to base register.
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LDR (Base+Offset)
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STR (Base+Offset)
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LEA (Immediate)
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Example
Address Instruction Comments
R1 PC 3 = x30F4 R2 R1 + 14 = x3102 M[PC - 5] R2 M[x30F4] x3102
1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1
x30F9
x30FA x30FB x30FC
0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0
0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1
opcode
R2 0
R2 R2 + 5 = 5 M[R1+14] R2 M[x3102] 5 R3 M[M[x30F4]] R3 M[x3102] R3 5
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Control Instructions
Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch
branch is taken if a specified condition is true signed offset is added to PC to yield new PC else, the branch is not taken PC is not changed, points to the next sequential instruction
TRAP
changes PC to the address of an OS service routine routine will return control to the next instruction (after TRAP)
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Condition Codes
LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times
Based on the last instruction that altered a register
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Branch Instruction
Branch specifies one or more condition codes. If the set bit is specified, the branch is taken.
PC-relative addressing: target address is made by adding signed offset (IR[8:0]) to current PC.
Note: PC has already been incremented by FETCH stage.
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BR (PC-Relative)
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R1 x3100 R3 0 R2 12
R2=0?
NO
YES
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Sample Program
Address Instruction Comments
R1 x3100 (PC+0xFF) R3 0 R2 0 R2 12 If Z, goto x300A (PC+5) Load next value to R4 Add to R3 Increment R1 (pointer)
1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1
X3008
x3009
0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0
Decrement R2 (counter)
Goto x3004 (PC-6)
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JMP (Register)
Jump is an unconditional branch -- always taken.
Target address is the contents of a register. Allows any target address.
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TRAP
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Another Example
Count the occurrences of a character in a file
Program begins at location x3000 Read character from keyboard Load each character from a file
File is a sequence of memory locations Starting address of file is stored in the memory location immediately after the program
If file character equals input character, increment counter End of file is indicated by a special ASCII value: EOT (x04) At the end, print the number of characters and halt
(assume there will be less than 10 occurrences of the character)
A special character used to indicate the end of a sequence is often called a sentinel.
Useful when you dont know ahead of time how many times to execute a loop.
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Flow Chart
Count = 0
(R2 = 0)
Done?
(R1 ?= EOT)
YES
NO
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Program (1 of 2)
Address Instruction Comments
R2 0 (counter) R3 M[x3012] (ptr) Input to R0 (TRAP x23) R1 M[R3] R4 R1 4 (EOT) If Z, goto x300E R1 NOT R1 R1 R1 + 1
0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1
X3008
x3009
0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1
R1 R1 + R0
If N or P, goto x300B
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Program (2 of 2)
Address Instruction Comments
R2 R2 + 1 R3 R3 + 1 R1 M[R3] Goto x3004 R0 M[x3013] R0 R0 + R2 Print R0 (TRAP x21) HALT (TRAP x25)
0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1
X3012
x3013
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Memory
Control and data registers for memory and I/O devices memory: MAR, MDR (also control signal for read/write)
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Register File
Two read addresses (SR1, SR2), one write address (DR) Input from bus result of ALU operation or memory read Two 16-bit outputs used by ALU, PC, memory address data for store instructions passes through ALU
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