MSSP

I 2C

SPI and I2C
The MSSP module uses six registers for IC operation.
SSPCON;
SSPCON2;
SSPSTAT;
SSPBUF;
SSPSR; and
SSPADD.

I2C
The Master Synchronous Serial Port module is a serial interface, used for communicating with
other peripheral or microcontroller devices.
These peripheral devices may be serial EERPOMs, shift registers, display drivers , A/D converters,
etc.
The MSSP can operate in any one of the two modes.
Serial Peripheral Interface(spi)
Inter integrated circuit(I2C)
Similar to serial communication in SPI mode, data transfer in IC mode is synchronous and
bidirectional. This time only two pins are used for data transfer. These are the SDA (Serial Data)
and SCL (Serial Clock) pins.
How transmission or reception is
initiated?
When master and slave components are synchronized by the clock, every data exchange is
always initialized by master.
Once the MSSP module has been enabled, it waits for a Start condition to occur.
First the master device sends the START bit (logic zero) through the SDA pin, then the 7-bit
address of the selected slave device, and finally, the bit which requires data write (0) or read (1)
to that device.
Accordingly, following the start condition, the eight bits are shifted into the SSPSR register. All
slave devices share the same transmission line and all will simultaneously receive the first byte,
but only one of them has the address to match.
Once the first byte has been sent (only 8-bit data are transmitted), master goes into receive
mode and waits for acknowledgment from the receive device that address match has occurred.
If the slave device sends acknowledge data bit (1), data transfer will be continued until the
master device (microcontroller) sends the Stop bit.
Start and Stop Condition
According to the I2C specification, all changes on the SDA line must occur while the SCL line is
low. Data is valid when SCL is high.
This restriction allows two unique conditions to be detected on the bus; a START sequence (S)
and a STOP sequence (P). A START sequence occurs when the master device pulls the SDA line
low while the SCL line is high. The START sequence tells all Slave devices on the bus that address
bytes are about to be sent.
The STOP sequence occurs when the SDA line goes high while the SCL line is high and it stops the
transmission.
Bits Transmitted.


Fig. 6-21 Data Transfer
Setting up the I2C
/*
Function: I2CInit
Return:
Arguments:
Description: Initialize I2C in master mode, Sets the required baudrate
*/
void I2CInit(void)
{
TRISC3 = 1; /* SDA and SCL as input pin */
TRISC4 = 1; /* these pins can be configured either i/p or o/p */
SSPSTAT |= 0x80; /* Slew rate disabled */
SSPCON = 0x28; /* SSPEN = 1, I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) */
SSPADD = 0x28 /* 100Khz @ 4Mhz Fosc */
}

/*
Function: I2CStart
Return:
Arguments:
Description: Send a start condition on I2C Bus
*/

void I2CStart()
{
SEN = 1; /* Start condition enabled */
while(SEN); /* automatically cleared by hardware */
/* wait for start condition to finish */
}

/*
Function: I2CStop
Return:
Arguments:
Description: Send a stop condition on I2C Bus
*/
void I2CStop()
{
PEN = 1; /* Stop condition enabled */
while(PEN); /* Wait for stop condition to finish */
/* PEN automatically cleared by hardware */
}

/*
Function: I2CRestart
Return:


Arguments:
Description: Sends a repeated start condition on I2C Bus
*/
void I2CRestart()
{
RSEN = 1; /* Repeated start enabled */
while(RSEN); /* wait for condition to finish */
}

/*
Function: I2CAck
Return:
Arguments:
Description: Generates acknowledge for a transfer
*/
}

void I2CAck()
{
ACKDT = 0; /* Acknowledge data bit, 0 = ACK */
ACKEN = 1; /* Ack data enabled */
while(ACKEN); /* wait for ack data to send on bus */
}

/*
Function: I2CNck
Return:
Arguments:
Description: Generates Not-acknowledge for a transfer
*/
void I2CNak()
{
ACKDT = 1; /* Acknowledge data bit, 1 = NAK */
ACKEN = 1; /* Ack data enabled */
while(ACKEN); /* wait for ack data to send on bus */


/*
Function: I2CWait
Return:
Arguments:
Description: wait for transfer to finish
*/
void I2CWait()
{
while ((SSPCON2 & 0x1F ) || ( SSPSTAT & 0x04 ) );
/* wait for any pending transfer */
}

/*
Function: I2CSend
Return:
Arguments: dat - 8-bit data to be sent on bus
data can be either address/data byte
Description: Send 8-bit data on I2C bus
*/

void I2CSend(unsigned char dat)
{
SSPBUF = dat; /* Move data to SSPBUF */
while(BF); /* wait till complete data is sent from buffer */
I2CWait(); /* wait for any pending transfer */
}

/*
Function: I2CRead
Return: 8-bit data read from I2C bus
Arguments:
Description: read 8-bit data from I2C bus
*/
unsigned char I2CRead(void)
{
unsigned char temp;
/* Reception works if transfer is initiated in read mode */
RCEN = 1; /* Enable data reception */
while(!BF); /* wait for buffer full */
temp = SSPBUF; /* Read serial buffer and store in temp register */
I2CWait(); /* wait to check any pending transfer */
return temp; /* Return the read data from bus */
} - See more at: http://www.8051projects.net/i2c-twi-tutorial/pic-i2c-code-example.php#sthash.hSmsi2OL.dpuf

Slave Mode Block Diagram
Clock Stretching
The slave is allowed to hold the SCL line low! This is called clock stretching. When the slave gets
the read command from the master it holds the clock line low. The microprocessor then gets the
requested data, places it in the transmission register and releases the clock line allowing the
pull-up resistor to finally pull it high. From the masters point of view, it will issue the first clock
pulse of the read by making SCL high and then check to see if it really has gone high. If its still
low then its the slave that holding it low and the master should wait until it goes high before
continuing. Luckily the hardware I2C ports on most microprocessors will handle this
automatically.