Presented

by
Ronald Collett
Numetrics Management Systems
Santa Clara, CA
www.numetrics.com
Key Performance Indicators
Of Methodology Capabilities
Measuring Design Productivity is the Foundation
of Assessing Design Methodology Capabilities
Design productivity is a proxy for design process
quality
High productivity means high design output per engineer
High productivity is a reflection of:
Engineering skill and management skills,
Tools, flows, methodology, infrastructure

To be used as a proxy, productivity calculation
must contemplate that the product designed is
released to volume production
Releasing to volume production implies that the product itself
offers the requisite functionality, performance, price,
reliability, form factor, etc. (i.e. the right value proposition)
Basic Productivity Definition
PRODUCTIVITY =
OUTPUT
LABOR INPUT
Measuring Manufacturing Productivity Is
Straightforward
MANUFACTURING
PRODUCTIVITY
VALUE-ADDED
LABOR INPUT
=
VALUE-ADDED = PRODUCT SELLING PRICE - COST OF MATERIALS
Measuring Design Productivity Is Much
More Difficult
????????
Effort (Person-weeks)
=
DESIGN
PRODUCTIVITY
Dissecting the Numerator of the Design Productivity
Metric--Whats the Best Measure of What a Design Team
Produces?
Overly simplistic and INACCURATE measure of what a
design team produces: Total transistors in the design

EFFORT (MAN-WEEKS)
TOTAL TRANSISTOR COUNT
There is Almost Zero Correlation between
Transistor Count and Project Effort
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Raw Transistors in Millions
Relationship Between Raw Transistors and Project Effort*
R
2
= 0.105
p = 0.008
= IC Design Project

0
500
1,000
1,500
2,000
2,500
3,000
3,500
0 2 4 6 8 10 12 14 16
Measuring Design Productivity
P =
Design
Output
Design
Effort
Units Influencing Factors
Factors that explain high
or low productivity:
- Engineering Skill Levels
- EDA Tools
- Design Flow
- Process Stability
- Customer Relationship
- Management Support
- Etc...
Transistor Count
Circuit Type
Reuse Levels
Timing
Density
Etc.
Numetrics Complexity
Units (NCUs)
Person-Weeks
(Direct Measure
Of Staff & Schedule)
A Very Strong Correlation Exists Between
Numetrics Complexity Unit (NCU) Calculation
and Project Effort
Numetrics Complexity Units (NCUs) in Millions
Y = 179 + 544 * X
R
2
= 0.520
p = 0.000
Relationship Between
NCUs and Project Effort*
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0
500
1,000
1,500
2,000
2,500
3,000
3,500
0 0.5 1 1.5 2 2.5 3 3.5
Numetrics Normalization Methodology Yields an R-squared
Value of 0.52 (Project Effort vs. NCUs/Chip)
Accuracy of the Normalization Methodology

R
2
= 0.105
p = 0.008
Actual Transistors per chip (Millions)
Project Effort
(Person-weeks)
NCUs per chip (Millions)
Actual Transistor Count
vs. Project Effort
Project Effort
(Person-weeks)
Numetrics Complexity Unit Count
vs. Project Effort
= IC Design Projects
R
2
= 0.520
p = 0.000
= IC Design Projects
0
500
1,000
1,500
2,000
2,500
3,000
3,500
0 2 4 6 8 10 12 14 16
0
500
1,000
1,500
2,000
2,500
3,000
3,500
0 1 2 3
Low Productivity Project
High Productivity Project
Comparing Design Capability
With DPMS
Comparing Design Capability
Without DPMS
Numetrics Design Productivity Management System
(DPMS) Quantifies Design Productivity and, therefore,
Design Quality
High Productivity
Design Project
Low Productivity
Design Project
Other Factors Explain the Difference in Design
Effort Between Projects of Similar Complexity
Engineering Capability
Inherent Design Complexity
Leadership
EDA Tools/Flows/Methodology
External Factors
69%
39%
IC Design
Effort
Key Performance Indicators are a Prerequisite
for Determining Quality of Design Process
IC Design Productivity IC Development Cost
IC Reuse Leverage IC Design Capacity
0 5000
500 4500
1000 4000
1500
3500
2000
2500
3000
$0
$20
$40
$60
$80
0
20000
2000
18000
4000 16000
6000
14000
8000
10000
12000
0%
20%
40% 60%
80%
100%
NCUs per
person week
Percent
Effort
Saved per
IC Design
Dollars per
NCors
$100
Performance
of a Particular Project
Industry Average
NCU= Numetrics Complexity Unit
NCUs per week
The Power of Measuring Design Process Quality by
Observing Three Key Performance Indicators
Simultaneously
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Design Productivity (Log Scale)
(NCUs designed per Person-Week)
ASSP Project Distribution by Design Productivity, Design Capacity & Development Cost*
Design Productivity Industry Average
5% Trim Mean
Design Capacity Industry Average
5% Trim Mean
Low-Cost Project
(Dev Cost < $5.55)
Mid-Cost Project
($5.55 < Dev Cost < $13.40
High-Cost Project
(Dev Cost > $13.40)
100
1,000
10,000
100,000
10 100 1,000 10,000 100,000
Dev. Cost=$ per NCU
Comparing the Quality of Two Different Design Flows
Design Capacity
(NCUs designed
per week)
LOW
HIGH
Design Productivity
(NCUs designed per Person-Week)
LOW HIGH
Average Productivity
Average Capacity
OLD Design Flow NEW Design Flow
NCU= Numetrics Complexity Unit
Two Steps are Needed to Compare
Different Chip Design Projects
1. Design complexity normalization is used to
Account for differences in reuse levels, circuit
types, process technology, timing, and other
circuit design characteristics.

2. Grouping similar projects by design application,
project scope, team goals, etc.
Combining Normalization with Grouping of Similar
Projects (in terms of design application, circuit content,
etc.) Provides for Best-in-Class Assessment
Low Cost Project
Best-in-Class
Quadrant
Design Capacity
(NCUs designed
per Week)
LOW
HIGH
Design Productivity
(NCUs designed per Person-Week)
LOW HIGH
Average Productivity
Average Capacity
Mid-Cost Project High Cost Project
Analog & Mixed-Signal ICs
for Communications
Applications
NCU= Numetrics Complexity Unit
Five Sets of Key Performance Metrics
Cycle Time Metrics
Project Effort Metrics
Project Cost Metrics
Design Reuse Metrics
Technology Metrics
Cycle Time Metrics
Design Capacity
NCUs /Week (Numetrics Complexity Units designed per
Week)
Design Cycle Time
Time from Project Start to Release to Volume Production
Project Schedule Slippage
as a Percentage of Planned Schedule
First Prototype Turnaround Time
1st Tapeout to 1st Packaged Prototypes Received from Fab
Time Allocation by First Tapeout
Time Consumed Prior to 1st Tapeout
Time Consumed After 1st Tapeout
DPMS Yields a Profile of Project Effort and
Duration for Each Design Phase
Project Duration = End Date - Start Date
Example Project Staffing Profile
(People versus Time)
Industry Standard
Definition
Project Effort = (Phase Duration FTE)
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0
5
10
15
Project
Start
Milestone
1
Project
End
Phase 1
First Tapeout*
Industry Standard
Definition
Milestone
3
Milestone
4
Milestone
5
Milestone
2
Phase 2
Phase 3
Phase
4
Phase 6
P
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5

Engineering Managers are using DPMS to
Analyze Cycle Time Improvements
Phase Duration Improvement
Phase 1
High Level
Design &
Partitioning
Phase 2
RTL
Design
Phase 3
Logic
Design
Phase 4
Test Insertion
APR & Timing
Verification
Phase 5
1st Proto
Fabrication.
Phase 6
System
Validation
18.0
(17%)
20.3
(19%)
15.4
(14%)
9.5
(9%)
10.0
(9%)
34.5
(32%)
6.3
(26%)
5.6
(23%)
6.6
(27%)
24.5 Weeks
107.8 Weeks
1.7
(7%)
2.3
(9%)
2.0
(8%)
Projects
Started
in 1996
-28%
CAGR
-33%
CAGR
-49%
CAGR
-35%
CAGR
-39%
CAGR
-40%
CAGR
TTM REDUCTION
-37% CAGR
Projects
Started
in 1999
Cycle Time Metrics (contd)
Design Phase Improvements
(if a standard template is used)

Relative Capacity (for netlist-handoff ASIC only)
Physical Design Cycle Time
Number of Silicon Spins
No. of Planned Spins
Actual Metal-only Spins & Actual All-layer Spins

Summary and Conclusions
Measuring design productivity is the cornerstone
for measuring design methodology efficacy

Quantifying design complexity is a prerequisite to
measuring design productivity--requires a robust
normalization approach in order to compare
designs fairly

Numetrics measurement system is now being used
across the semiconductor and systems industry

Quality of design process has become tantamount
to quality of manufacturing process