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This document compares and contrasts CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) architectures. CISC uses large, complex instructions that can perform multiple operations in one instruction, while RISC uses simpler instructions that are optimized to perform single operations. Historically, CISC was developed when memory was slow and expensive, so complex instructions reduced memory accesses. Later, RISC emerged as memory speeds increased and studies showed CISC instructions went underutilized. CISC trades off more cycles per instruction for fewer instructions total, while RISC aims to minimize cycles per instruction at the cost of more total instructions. Examples show a multiplication operation requiring one instruction in CISC versus four instructions in
This document compares and contrasts CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) architectures. CISC uses large, complex instructions that can perform multiple operations in one instruction, while RISC uses simpler instructions that are optimized to perform single operations. Historically, CISC was developed when memory was slow and expensive, so complex instructions reduced memory accesses. Later, RISC emerged as memory speeds increased and studies showed CISC instructions went underutilized. CISC trades off more cycles per instruction for fewer instructions total, while RISC aims to minimize cycles per instruction at the cost of more total instructions. Examples show a multiplication operation requiring one instruction in CISC versus four instructions in
This document compares and contrasts CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) architectures. CISC uses large, complex instructions that can perform multiple operations in one instruction, while RISC uses simpler instructions that are optimized to perform single operations. Historically, CISC was developed when memory was slow and expensive, so complex instructions reduced memory accesses. Later, RISC emerged as memory speeds increased and studies showed CISC instructions went underutilized. CISC trades off more cycles per instruction for fewer instructions total, while RISC aims to minimize cycles per instruction at the cost of more total instructions. Examples show a multiplication operation requiring one instruction in CISC versus four instructions in
Universidad Nacional de Colombia Sede Manizales 14 de Agosto de 2012 1 Meaning and characteristics of CISC Both refers to the machine (microprocessor) instruction set architecture ISA.
CISC: Complex instruction set computer. large instruction set instructions can perform very complex operations, powerful assembly language variable instruction formats large number of addressing modes few registers machine instructions implemented with microcode
2 Meaning and characteristics of RISC RISC: Reduced instruction set computer. relatively few instructions simple addressing modes, only load/store instructions access memory uniform instruction length many registers no microcode pipelined instruction execution 3 History I In the beginning the memory was an invaluable resource, and the access time was pretty slow, so the instructions was powerful enough to develop complex operations and only occupy one memory space, which only had to be acceded one time, this was the principal goal of CISC, additionally the reduction of semantic gap and the incipiency of compilers was a problem to overcome. 4 History II The advance in memory speed and studies that demonstrated that a wide part of the CISC instructions was actually unused leaded to the research of a computing based in elemental instructions and pipelined execution. 5 Processor performance The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program 6 Comparison 7 CISC RISC Emphasis on hardware Emphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only
Memory-to-memory: "LOAD" and "STORE" incorporated in Instructions Register to register: "LOAD" and "STORE" are independent instructions Small code sizes, high cycles per second Low cycles per second, large code Sizes Transistors used for storing complex Instructions Spends more transistors on memory registers
Machines Using CISC and RISC Architectures CISC: Intel 80486
RISC: ARM MIPS PowerPC 8 Example: CISC Approach for a product of two operands
CISC Approach CISC design would try to finish the task in the minimum possible instructions by implementing hardware which could understand and execute series of operations. Thus the processor would come with a specific instruction MUL in its instruction set. MUL will loads the two values from the memory into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate location. So, the entire task of multiplying two numbers can be completed with one instruction: MUL 1:3, 4:2 MUL is referred to as a "complex instruction" as it operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions. 9 Example:RISC Approach for a product of two operands
RISC processors use simple instructions that can be executed within a clock cycle. Thus, MUL instruction will be divided into three instructions. i) "LOAD," which moves data from the memory bank to a register, ii) "PROD," which finds the product of two operands located within the registers, and iii) "STORE," which moves data from a register to the memory banks. In order to perform the task, a programmer would need to code four lines of assembly: LOAD A, 1:3 LOAD B, 4:2 PROD A, B STORE 1:3, A 10 Bibliography http://www.engineersgarage.com/articles/risc- and-cisc-architecture http://users.abo.fi/mats/codeopt2011/handouts /Processors.pdf Example 11 Thanks Questions 12
Chapter 06 Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) 5th Edition