Greater Than(A>B)
Eg : A1 A0
B1 B0
1
0
0
1
1
1
1
0
0
1
0
0
1. If A1=1 and B1=0 then A>B
A>B : A1B1+
Greater Than(A>B)
Eg : A1 A0
1
0
1
1
B1 B0
0
1
1
0
Less Than(A<B)
Eg : A1 A0
B1 B0
10
0
01
1
1
0
1
1
0
0
0
1
1. If A1=0 and B1=1 then A<B
A<B : A1B1+
Less Than(A<B)
Eg :
A1 A0
0
0
1
0
1
0
0
0
B1 B0
1
1
1
1
1 1
0
1
Equal(A=B)
Eg : A1 A0
0
0
1
1
0
0
0
0
0
B1 B0
1
1
11 1
0
1
0 0
Greater than(A>B)
1. If A3=1 and B3=0, then A>B or
2. If A3 and B3 are coincide, and if A2=1 and B2=0,
then A>B or
3. If A3 and B3 are coincide, and A2 and B2 are
coincide, and if A1=1 and B1=0, then A>B or
4. If A3 and B3 are coincide, and A2 and B2 are
coincide, and if A1 and B1 are coincide, and if
A0=1 and B0=0, then A>B
A>B:A3B3+(A3 * B3)A2B2+(A3 * B3)(A2 * B2)A1B1
+(A3 * B3)(A2 * B2)(A1* B1)A0B0
Less than(A<B)
1. If A3=0 and B3=1, then A<B or
2. If A3 and B3 are coincide, and if A2=0 and B2=1,
then A>B or
3. If A3 and B3 are coincide, and A2 and B2 are
coincide, and if A1=0 and B1=1, then A<B or
4. If A3 and B3 are coincide, and A2 and B2 are
coincide, and if A1 and B1 are coincide, and if
A0=0 and B0=1, then A<B
A<B:A3B3+(A3 * B3)A2B2+(A3 * B3)(A2 * B2)A1B1
+(A3 * B3)(A2 * B2)(A1* B1)A0B0
Equal(A=B)
If A3 and B3 coincide and if A2 and B2 coincide
and if Al and B1 coincide and if A0 and B0
coincide, then A = B.
A = B: (A3 B3) (A2 B2) (A1 B1) (A0 B0)
Encoders
A digital circuit that produces a binary output
code depending on which of its inputs are
activated.
An Encoder produces m bit binary code
corresponding to the digital input number
n
input
lines
Encoder
m
output
lines
Octal Digits
Binary
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
Octal Digits
Binary
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
A2= D4+D5+D6+D7
Octal Digits
Binary
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
A1= D2+D3+D6+D7
Octal Digits
Binary
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
A0= D1+D3+D5+D7
A2=D4+D5+D6+D7
A1=D2+D3+D6+D7
A0=D1+D3+D5+D7
Decimal
Digits
Binary
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Decimal
Digits
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A3= D8+D9
Binary
Decimal
Digits
Binary
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A2= D4+D5+D6+D7
Decimal
Digits
Binary
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A1= D2+D3+D6+D7
Decimal
Digits
Binary
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0= D1+D3+D5+D7+D9
A3 = D8+D9
A2 = D4+D5+D6+D7
A1 = D2+D3+D6+D7
A0 = D1+D3+D5+D7+D9
Decoder
A decoder is a logic circuit which converts a Nbit binary input into M output lines such that
only one output line is activated for each one
of the possible combination of inputs.
2-Line-to-4-line Decoder
3Lineto-8-Line Decoder
Multiplexers
A multiplexer (MUX) or data selector is a logic
circuit that accepts several data inputs and
allows only one of them at a time to get
through to the output. The routing of the
desired data input to the output is controlled
by SELECT inputs.
4-Input Multiplexer
UNIT -IV
Sequential Logic
Combinational Logic
Output depends only on current input
Ex: Adders, Substractors etc.
Sequential Logic
Output depends not only on current input but
also on past input values.
Need some type of memory to remember the
past input values.
Flip-Flop
The memory element used in clocked sequential
circuit are called flip-flop.
These cells are binary cells capable of storing one
bit of information.
A flip-flop circuit has two output.
Normal Output
Complement Output
Clocked RS Flip-Flop
When the clock pulse(CP=0) is zero, the outputs of the two AND gates will
be remains 0.
When the clock pulse (CP=1) is one, the input values of S and R are allowed
to reach the basic flip-flop.
When S=1, R=0, and CP=1, the set value(I,e, S=1) allowed to reach the basic
flip-flop.
When S=0,R=1 and CP=1, the reset value (I.e, R=1) allowed to reach the
basic flip-flop.
When the S=1,R=1 and CP=1, the output will go to 0.
When the CP is removed, the output of the flip flop may goto either 0 or 1.
D Flip-Flop
Transition Table
JK Flip-Flop
When J=K=0
When both J and K are 0, the clock pulse has no effect on the output and
the output of the flip-flop is the same as its previous state. This is because
when both the J and K are 0, the output of their respective AND gate
becomes 0.
When J=0,K=1
When J=0, the output of the AND gate corresponding to J becomes 0 (i.e.)
S=0 and R=1. Therefore Q becomes 0. This condition will reset the flipflop. This represents the RESET state of Flip-flop.
When J=1,K=0
In this case, the AND gate corresponding to K becomes 0(i.e.) S=1 and R=0.
Therefore Q becomes 0. This condition will set the Flip-flop. This
represents the SET state of Flip-flop.
When J=K=1
Consider the condition of CP=1 and J=K=1. This will cause the output to
complement again and again. This complement operation continues until the
Clock pulse goes back to 0.
T Flip-Flop
Q
Shift Register
A register is a group of memory elements that
work together as a unit to store a word by
shifting its bits left or right.
A Shift register moves the stored bits of binary
information either left or right. This bit
shifting is essential for certain arithmetic and
logic operations used in microprocessors.
Shift Left
Shift Right
Excitation table