(dsPic30f4011)
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Introduce to interrupts
Interrupts in ds PIC
Interrupts Priority
Reset Sequence
Traps
Interrupts Sequence
Alternate Interrupt Vector Table
External Interrupt Requests
Fast Context Saving
Interrupts Nesting
Wake-up from Sleep and Idle
Homework
Reference Manual.
1. Introduce to interrupts
<? >What is an interrupt?
An interrupt is a little piece of hardware that sits,
waiting to detect a trigger event, such as a particular pin
going from a low state to a high state.
2. Interrupts in (ds)PIC
The dsPIC30f4011/4012 has 30 interrupt sources and 4
processor exceptions
Interrupt Source : External Interrupt, Input Capture, Output
Compare, Timer , UART Receiver ( transmitter ) , ADC
Convert Done, I2C , SPI, Combined IRQ for CAN, FLTA
PWM Fault A
Special Function Registers
- IFSx ( 3 registers )
- IECx ( 3 registers )
- IPCx ( 12 registers )
- IPLx ( 1 registers)
- INTCONx ( 2 registers )
3. Interrupts priority
Interrupt Piority bits for each individual interrupt
source are located 3 bits of each nibble within the IPCx
register
Natural Order Priority
- determined by the position of an interrupt in the
vector table
- only affects interrupt operation when multiple
interrupts with the same user-assigned priority become
pending at the same time.
Note: the user can assign a very high overall priority level
to an interrupt with a low natural order priority
4. Reset Sequence
A Reset is not a true exception
Reset sources : 5 sources of error caused a
device reset
- Watchdog Time-out
- Uninitialized W Register Trap
- Illegal Instruction Trap
- Brown-out Reset (BOR)
- Brown-out Reset (BOR)
5. Traps
non-maskable interrupts
8 fixed priority levels for
traps, Level 8 through
Level 15
Trap sources :
- Math Error Trap(level 11)
- Address Error Trap(level 13)
- Stack Error Trap(level12)
- Oscillator Fail Trap(level 14)
6. Interrupt Sequence
All interrupt event flags are sampled in the
beginning of each instruction cycle by the
IFSx registers
The Interrup request ( IRQ ) will cause an
interrupt to occur if the corresponding bit in
the interrupt enable (IECx) register is set
Note :
- The user can always lower the priority level by
writing a new value into SR. The Interrupt
Service Routine must clear the interrupt flag bits
in the IFSx register before lowering the processor
interrupt priority in order to avoid recursive
interrupts.
- The IPL3 bit is always clear when interrupts are
being processed. It is set only during execution of
traps.
INTCON1 Register
o
o
o
o
o
o
o
o
o
INTCON2 register
IFS0 Register
IPC0 Register
13. Excersies
1. Vit chng trnh
Vit chng trnh khi to 2 ngt:
; -Ngt ngoi 0 vi u tin cao.
; -Ngt timer 0 vi u tin thp.
; -Ngt INT0 : bt 3 led n RB1, RB2, RB3 sng cng ;lc
; -Ngt timer0 : tt 3 led n RB1, RB2, RB3 sau 1s hin th
k t ln LCD.
2. Chng trnh to xung vung c chu k T=0.01 giy,
rng 50%, s dng thch anh tn s 4Mhz:
3. Chng trnh m xung ngoi a ti chn RB0 (chn ngt
ngoi) hin th s m t 0-99 trn cc led n ni vi
PORTC.