Prof.

Atal Chaudhuri
Dept. of Computer Sc. & Engg.
Jadavpur University
1

8086 INTERNAL CONFIGURATION

AX

Data Registers
AH
AL

BX

BH

BL

CX

CH

CL

DX

DH

DL

ALU

( Address / Data )
Instruction Queue
Control
Logic

20 pins
( Control )
20 pins

Index Registers and

Pointers
SP

PSW

Segment Registers
CS

BP

SS

SI

DS

DI

ES

IP

+ 5 volts

Ground

Clock
5MHz / ( 8 , 10 )

The internal registers of 8086 can be divided into three groups :

i.

Data Registers.

ii.

Pointers & Index Registers.

iii.

Segment Registers.

And Instruction Pointer Flag Registers or PSW.

Data Registers :
AX , BX , CX , DX

Used to store operands and results.

Can be used as 16-bit registers.

Can be used as two separate 8-bit registers.

AX

AH , AL

BX

BH , BL

CX

CH , CL

DX

DH , DL

Some special use of the data register :

AX

as

Accumulator.

BX

as

Base register in memory address calculation.

CX

as

Counter.

DX

as

I / O address.

At any instant memory space is divided into maximum four segments :

May be distinct segments.

May be overlapping segments.

Maximum 64 KB long.

Begins at a 16 byte boundary.

The advantages of using segment registers are :

1.

Allow the memory capacity to be 1 MB, even though the address operands are 16-bits wide.

2.

Allow the instruction, data or stack portion of a program to be more than 64 KB long by using
more than one code, data or stack segment.

3.

Facilitate the use of separate memory areas for a program, its data and the stack.

4.

Permit a program and / or its data to be put into different areas of memory each time the program
is executed ( highly useful in time sharing multiprogramming environments ).

CS, The Code Segment :

It points to the segment that holds the program currently being executed.
( CS ) x 1610 + ( IP ) derives the memory address of the next instructions to be
executed.

SS, The Stack Segment :

It points to the current Stack segment in conjunction with SP or BP.
Stack is a data structure in memory that functions as a temporary depository for data and addresses.

DS, The Data Segment :

It points to the current Data segment, which usually holds program variables.

ES, The Extra Segment :

It points it the current Extra segment which is used in string operations and also may override DS.

Segment over_ride table showing default and alternate segment base for memory referenced instructions.
Type of memory ref.

Default Segment

Alternate Segment

Offset

Instruction Fetch

CS

None

IP

Stack Operation

SS

None

SP

Any base reg. other than BP

DS

CS,ES,SS

Effective address

String source

DS

CS,ES,SS

SI

String Destination

ES

None

DI

BP as base register

SS

CS,ES,DS

MOV AX, [BX]

MOV AX, ES: [BX]

Effective address

((DS) x 16 + (BX)) (AX)

((ES) x 16 + (BX)) (AX) ( Default segment reg. DS is

overridden by ES )

To provide flexible base addressing and indexing, a data address may be formed by adding together
a combination of the BX or BP register contents, SI or DI register contents and a displacement. The
result of such an address computation is called an Effective Address ( EA ) or Offset . The final
data address, however, is determined by the EA and the appropriate Data segment ( DS ), Extra
segment ( ES ) or stack segment ( SS ) register.

Formation of physical address :

Effective Address

or

Offset

16 bits

Segment Address

16 bits

Physical Address

20 bits

Example :

431B
+ 123A0

Effective Address
Beginning Segment Address

157BB

In accessing the stack segment the 8086 gets the base address from SS and the offset from one of the
pointer register SP or BP.

In accessing the data segment the 8086 gets the base address from DS and the offset BX or one of the
index registers SI or DI and also BP.

( Normally, 8086 assumes these registers combinations but one can override these assignments. For
instance, one can access a location in the extra segment by directing the 8086 to apply ES rather than
SS to an offset in BP ).

Instruction Pointer :
General operation cycle for a computer is as follows :
1.

Fetching the next instruction from the address indicated by the PC.

2.

Putting it in the instruction register and decoding it while the PC is incremented to point to the
next instruction.

3.

Executing the instruction and if a branch is to be taken resetting the PC to the branch address.

4.

Repeating steps 1 through 3.

8086 follows the same basic pattern but here some of the operations may be overlapped.
The address of the next instruction is determined by the sum of the ( IP ) and ( CS ) X16 10 and the
instruction register is a 6 byte FIFO queue that is continually being filled whenever the system
bus is not needed for some other operation. This look ahead feature significantly increases the
CPU throughput except when branching takes place.
8086 CPU has two units EU ( Execution Unit ) and BIU ( Bus Interface Unit ).
BIU fetches the instruction and EU executes with the help of ALU under control of Control Unit.
( 8088 instruction queue is 4-byte wide )

Programme Status Word ( PSW ) & Flag Bits :

8086s PSW contains 16 bits but 7 of them are not used. Each bit of PSW is called a flag. The flags
are divided into the conditional flags which reflect the result of the previous operation involving the
ALU, and the control flags which control the execution of some special functions.

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

X

OF DF IF TF SF ZF X AF X PF X CF

Bit 0, The Carry Flag ( CF ) :

An addition causes this flag to be set if there is a carry out of the MSB, and a subtraction causes it to
be set if a borrow is needed. Some other instructions also affect this flag.

Bit 2, The Parity Flag ( PF ) :

It is set to 1 if the low order 8 bits of the result contain even number of 1s, otherwise it is cleared.

Bit 4, The Auxiliary Carry Flag ( AF ) :

It is similar to the CF bit except AF reflects the presence of a carry or borrow out of bit 3 of the
operand.

Bit 6, The Zero Flag ( ZF ) :

It is 1 if the result of an operation is zero. A non-zero result clears ZF to 0.

10

Bit 7, The Sign Flag ( SF ) :

It reflects the MSB of the result regardless of whether the result is 8-bit or 16-bit long. ( Since in 2s
complement MSB represents the sign of the number ).

Bit 8, The Trap Flag ( TF ) :

If set, a trap ( non maskable interrupt ) is executed after each instruction i.e. 8086 is put in single
stepping mode for debugging purpose.

Bit 9, The Interrupt Enable Flag ( IF ) :

If set, the maskable type interrupt can be recognized by the CPU, otherwise, these interrupts are
ignored.

Bit 10, The Direction Flag ( DF ) :

Causes the 8086 to automatically decrement ( DF = 1 ) or increment ( DF = 0 ) the index registers after
a string instruction is executed.

If DF = 1 a string is processed from high address to low address or from right to left and vice-versa.

11

Bit 11 , The Overflow Flag ( OF ) :

It is set if there is an overflow from the MSB i.e. if the result is out of range.

OF is 1 if the addition of two like signed numbers, or the subtraction of two opposite signed
numbers, has produced a result that exceeds the 2s complement capacity of the operand, otherwise it
is 0.

OF is also 1 if the most significant bit ( sign bit ) of the operand is changed at any time during an
arithmetic shift operation, otherwise it is 0.

OF flag in combination with CF flag, also indicates the length of a multiplication result. If the upper
half of the product is non-zero, CF and OF are 1, otherwise both bits are 0.

Finally OF is 1 if the quotient produced by a divide operation overflow the result register.

12

Addressing Modes :
In assembly language each instruction may have maximum four fields :
[ Label ] Mnemonic / Opcode [ Operand ] [ Comment ]
Addressing modes used in data handling :

Immediate :
The datum is 8-bit or 16-bit long and is part of the instruction.
Instruction
Datum
Immediate

Direct :
The 16-bit effective address of the datum is part of the instruction.
Instruction

Memory

EA.

Datum
Direct

13

Register :
The datum is in the register that is specified by the instruction.
Instruction

Register

Register

Datum
Register

Register may be
AX , BX , CX , DX , SI , DI , SP , BP ,

for 16-bit

AH , AL , BH , BL , CH , CL , DH , DL ,

for 8-bit

14

Register Indirect :
The effective address of the datum is in any base register, index register or BX, i.e.

EA =

( BX )
( BP )
( SI )
( DI )

Instruction

Register

Memory

Register

EA.

Datum

Register Indirect

15

Register Relative :
The effective address is the sum of our 8-bit or 16-bit
displacement and the contents of a base register or an index
register.
EA =

( BX )
( BP )

8-bit displacement (sign extended) or 16-bit displacement

( DI )
( SI )
Instruction
Register

Displacement
Memory

EA.

Datum

Register
Address

Register relative

16

Based Index :
The effective address is the sum of the base register and an index register, both are specified by the
instruction i.e.
( BX )

( SI )

EA =

+
( BP )

( DI )

Instruction
Base reg.

Index reg.

Register
Index
Memory

EA.

Datum

Register
Base address

Based indexed

17

Relative Based Indexed :

The effective address is the sum of an 8-bit or 16-bit displacement and a based indexed address i.e.

( BX )
EA =

( SI )
+

( BP )

+ 8-bit displacement (sign extended) or 16-bit displacement

( DI )
Instruction

Base reg.

Index reg.

Displacement
Register
Index

Memory

EA

Datum

Register
Base address

Relative based indexed

18

Example :
( BX )

= 0158

( DI) = 10A5

Displacement =1B57

( DS) = 2100

And DS is used as the segment register, then the effective and physical address produced by these
quantities and the various addressing mode would be :
Direct : EA = 1B57
Physical address = 1B57 + 21000 = 22B57
Register : No effective address datum is in specified register.
Register indirect assuming register BX : EA = 0158
Physical address = 0158 + 21000 = 21158
Register relative assuming register BX : EA = 0158 + 1B57 = 1CAF
Physical address = 1CAF + 21000 = 22CAF
Based indexed assuming registers BX and DI : EA = 0158 + 10A5 = 11FD
Physical address = 11FD + 21000 = 221FD
Relative based indexed assuming BX and DI : EA = 0158 + 1B57 = 2D54
Physical address = 2D54 + 21000 = 23D54

19

Intrasegment Direct :The effective branch address is the sum of an 8-bit or 16-bit displacement and
the current contents of IP. When the displacement is 8 bits long, it is referred to as a short jump. It
may be used with either conditional or unconditional branching, but a conditional branch instruction
have only an 8-bit displacement.
Instruction
Displacement

IP

EA = Effective branch address

Intrasegment Direct
Intrasegment Indirect : The effective branch address is the contents of register or memory location
that is accessed using any of the above data addressing modes except the immediate mode. The
contents of IP are replaced by the effective branch address. This addressing mode may be used for
unconditional branch instructions.
Register
Effective branch address

Instruction
Addressing Mode

EA. computed according

to addressing mode

Or

Memory
Effective branch address

Intrasegment Indirect
.

EA is added to 1610 times the contents of the appropriate segment register.

20

Intersegment Direct : Replaces the contents of IP with a part of the instruction and the contents of
CS with another part of the instruction. The purpose of this addressing mode is to provide a means
of branching from one code segment to another.
Instruction
Offset

CS

Segment
IP

Intersegment Direct
Intersegment Indirect : Replaces the contents of IP and CS with the contents of two consecutive
words in memory that are referenced using any above data- related addressing modes except the
immediate and the register.
Two consecutive
words in memory
Instruction
Branch address Offset
.
EA computed according
Addressing Mode
Segment address
to addressing mode
Intersegment Indirect
.

EA is added to 1610 times the contents of the appropriate segment register.

21

Note that the physical branch address is the new content of the IP plus the content of CS multiplied
by 1610. An intersegment branch must be conditional.
To demonstrate how indirect branching works with some of the data addressing modes, suppose that
BX = 1256

SI = 528F

Displacement = 20A1.

Then :
With direct addressing, the effective branch addresses are the contents :
20A1 + ( DS ) x 1610.
With register relative addressing assuming register BX, the effective branch addresses
are the contents of :
1256 + 20A1 + ( DS ) x 1610.
With based indexed addressing assuming registers BX and SI, the branch are the
contents of :
1256 + 528F + ( DS ) x 1610.

22

Pin No. Symbol I/O,3-state Description

1
GND Ground
2-16
AD14-AD0

I/O-3

Outputs address during

(for 8088 AD15-AD8 are A15-A8
the first part of the bus
and are only for outputting
cycles and inputs or
address bits)
outputs data during the
remaining part of the
bus cycles.
17 NMI I
Non-maskable interrupt
request-positive edge
trigerred.
18 INTR I
Maskable interrupt
requestlevel triggered
19 Clock I
Clock-33.3% duty cycle,
(5MHz for 8088
maximum rate depends
8MHz for 8088-2)
on CPU model.
5MHz for 8086
8MHz for 8086-2
10MHz for 8086-1
23

Pin No. Symbol I/O,3-state Description

20
21

GND
Reset

22

Ready

Ground
Terminates current
activity, clears PSW, IP, DS,
ES, SS, and instruction
queue and sets CS to FFFF.
Thus processing begins from
FFFF0 when signal is
withdrawn. (Signal must be
high for at least 4 clock
cycles)
Acknowledgement from
memory or I/O interface
that CPU can complete the
current bus cycles. CPU
samples the ready input at
the rising edge of 3rd clock
of bus cycles, if finds high
continues otherwise wait
24
state is introduced.

Pin No. Symbol I/O,3-state Description

23

Test

32

RD

O/3

33

Min/Max

24-31

An input signal used in

conjunction with WAIT
instruction in multiprocessing environment. If
Test=1, the processor waits
in idle state during WAIT
instruction, except for
processing interrupts until
Test=0.
Definition depends on max
or min mode to be discussed
separately afterwards.
Indicates a memory or I/O
read is to be performed.
Min/Max = 1 means
minimum mode (single
processor) and Min/Max = 0
means multi-processor
25
environment.

Pin No. Symbol I/O,3-state Description

34

BHE/S7

O-3

During T1, BHE goes low if

byte transfer takes place
from an odd address on D8D15 or a word transfer takes
place from an even address
boundary on D0-D15.

BHE=1 indicates data transfer on D0-D7. During T2 to T4 signal S7

is available which is always zero (nothing is defined).

35-38
A19/S6 O-3
- A16/S3

During T1 of the bus cycles,

the upper 4-bits of the
address are output and
during T2-T4status is output.

S3 and S4 indicate the segment register being used as follows:

S4
S3
0
0
ES
0
1
SS
1
0
CS or none
1
1
DS
26
S5 gives the current setting of IR. S6 is always 0.

Pin No. Symbol I/O,3-state Description

39
40

AD15
Vcc

Minimum Mode:
24
INTA
25

ALE

26

DEN

I/O-3

Same as AD14-AD0.
+5volts + 10%.

O-3

Indicates recognition of an
interrupt request.
O
Address latch enable,
generated during T1 state of
bus cycles and address is
latched during the high to
low transition of ALE.
O-3
Data enable, active during
T2 to T4 of the bus cycles to
inform the transreceiver that
CPU is ready to send or
receive data.
27

Pin No. Symbol I/O,3-state Description

27

DT/R

O-3

28

M/IO

O-3

29

WR

O-3

30
31

HLDA
HOLD

(for 8088 it is M/IO)

O
I

Controls the direction of

data flow through the
transreceiver, 1 indicates
transmit write cycles and
0 indicates receive Read
cycle.
Distinguishes between
memory operation and I/O
operation.
When 0 indicates a write
operation is being
performed.
Hold acknowledge.
Hold request normally from
bus master/DMA controller.

28

Pin No. Symbol I/O,3-state Description

Maximum Mode:
24,25
QS1,QS0
instruction queue.

Reflects the status of the

00 - No instruction was taken from the queue.

01 - First byte of the current instruction was taken from the
queue.
10 - The queue was flashed because of a transfer instruction.
11 - A byte other than the first byte of an instruction was
taken from the queue.

26,27,28 S0,S1,S2

O-3

Indicates the type of

transfer to take place during the current bus cycle.
S2
0
0
0
0
1

S1
0
0
1
1
0

S0
0
1
0
1
0

Interrupt acknowledge The status becomes active

I/O Read
prior to beginning of a
I/O Write
bus cycle and returns to
Halt
inactive during later
Instruction fetch
later part of the cycle.
29

Pin No. Symbol I/O,3-state Description

S2
1
1
1

29

S1 S0
0
1
1
0
1
1

Memory Read
Memory Write
Inactive

LOCK

O-3

This pin gets activated

during LOCK prefixed
instructions.

When it is active low, this signal can be used to prevent other

processors from getting access to the system bus. The LOCK pin
remains low till the prefixed instruction is carried out. It is
connected with 8289 bus arbiter.

30

RQ/GT1

I/O

31

RQ/GT0

I/O

For inputting bus requests

and outputting bus grants.
Same as above but has
higher priority.
30

BHE (Byte High Enable)

Operation

BHE A0

Word transfer at
an even address
Byte transfer at
an even address
Byte transfer at
an odd address
Word transfer at
an odd address

Data pins used

AD15-AD0

AD7-AD0

AD15-AD8

0
1

1
0

Word transfer referenced from an even address boundary 16bits

of data from consecutive two memory locations are transferred
on D0-D15 in one bus cycle. However if word transfer is referenced
from an odd address boundary it takes two bus cycles.
AD15-AD8 (first bus cycle:puts the least significant byte on
AD15-AD8)
AD7-AD0 (next bus cycle:puts the most significant byte on
AD7-AD0)
31

INSTRUCTION SET
There are 92 basic instruction types. The instruction set can be divided into seven
functional groups.
1.

2.

3.

4.

5.
6.

7.

Data transfer instructions move information between registers and memory locations or
I / O ports.
Arithmetic instructions perform arithmetic operations on Binary and Binary Coded
Decimal ( BCD ) numbers.
Bit manipulation instructions perform shift, rotate, and logical operations on memory
locations and registers.
Control transfer instructions perform jumps, calls to procedures and returns from
procedures, to control the sequence in which a program executes.
String instructions move, compare and scan strings of information.
Interrupt instructions cause the microprocessor to be interrupted, so that it can service
some specific condition.
Processor control instructions set and clear status flags and change the microprocessors
execution state.

32

Data transfer instructions

Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

GENERAL -PURPOSE
MOV

MOV

destination,source

PUSH
POP
XCHG
XLAT

PUSH

source

POP
XCHG

destination
destination,source

XLAT

INPUT / OUTPUT
source-table
-

IN
OUT

IN
OUT

accumulator,port
port,accumulator

ADDRESS TRANSFER
LEA
LDS
LES
-

LEA

reg16,mem16

LDS
LES

reg16,mem32
reg16,mem32

33

Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

FLAG TRANSFER
LAHF
SAHF
PUSHF
POPF

NOTE:

LAHF
SAHF

PUSHF
POPF

- * *

* means changed and - means unchanged

34

Arithmetic instructions
Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

ADDITION
ADD
ADC
AAA
DAA
INC
SUB
SBB
AAS
DAS
*
DEC
NEG
CMP

ADD
ADC
AAA
DAA
INC

destination,source
destination,source

destination

*
*
?
?
*

- - - - - -

* *
* *
? ?
* *
* *

*
*
*
*
*

* *
* *
? *
* *
*

*
*
?
*

*
*
*
*

*
*
?
*

*
*
*

* * *
* * *
* * *

*
*
*

*
*

SUBTRACTION
SUB
SBB
AAS
DAS

destination,source
destination,source

*
*
?
?

DEC
NEG
CMP

destination
destination
destination,source

*
*
*

- - - -

*
*
?
*

35

Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

MULTIPLICATION
MUL
IMUL
AAM

MUL
IMUL
AAM

source
source

*
*
?

?
?
*

?
?
*

?
?
?

? *
? *
* ?

?
?

?
?

?
?

?
?

?
?

SIGN-EXTENSION
- - -

- - - - - - - - - - -

DIVISION
DIV
IDIV

DIV
IDIV

AAD

AAD

CBW
CWD

CBW
CWD

source
source

?
?
?

Note: * means unchanged and ? means undefined.

36

Bit manipulation instruction

Mnemonic

Assembler format

Flags

OF DF IF TF SF ZF AF PF CF

LOGICAL
AND

AND

destination,source

OR
0
XOR
0
NOT
SAL/SHL
TEST
SAR
*
SHR
*
ROL
ROR
RCL
ROR

OR

destination,source

XOR

destination,source

* 0

NOT
SAL
TEST
SAR

SHIFT
destination
destination,count
destination,source
destination,count

*
0
*

--

- -- -- -

- ** **
* *

??
?

- ** 0*
*

SHR

destination,countROTATE

ROL
ROR
RCL
ROR

destination,count
destination,count
destination,count
destination,count

*
*
*
*

- - - - -

- - - - -

- *
- *
- *
- *

Note: * means unchanged and ? means undefined.

37

Control transfer instructions

Mnemonic

Assembler format

Flags

OF DF IF TF SF ZF AF PF CF

ITERATION CONTROLS
LOOP
LOOPE /
LOOPZ
LOOPNE /
LOOPNZ
CALL
RET
JMP

LOOP

short-label

LOOPE

short-label

LOOPNE short-label

UNCONDITONAL TRANSFERS
CALL
RET
JMP

target
[pop-value]
target

- - - -

- - - -

- - - -

38

Mnemonic

Assembler format

Flags
OF DF IF TF SF ZF AF PF CF

CONDITIONAL TRANSFERS
JA / JNBE
JAE/ JNB
JB/JNAE/JC
JBE / JNA
JCXZ
JE / JZ
JG/JNLE
JGE /JNL
JL / JNGE
JLE /JNG
JNC
JNE /JNZ
JNO
JNP/ JPO
JNS
JO
JP/JPE
JS

JA
JAE
JB
JBE
JCXZ
JE
JG
JGE
JL
JLE
JNC
JNE
JNO
JNP
JNS
JO
JA
JA

short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label

- - - - - - - - - - - - - - - - - - 39-

The conditional transfer instructions

Instruction

Description

Jump if ...

JA
JAE
JB
JBE
JC

Jump If Above
Jump If Above or Equal
Jump If Below
Jump If Below or Equal
Jump If Carry

CF = 0 and ZF = 0
CF = 0
CF = 1
CF =1 OR AF = 1
CF =1

JCXZ
JE
*JG
*JGE
*JL

Jump If CX is zero
Jump If Equal
Jump If Greater
Jump If Greater or Equal
Jump If Less

(CX) = 0
ZF=1
ZF=0 and SF = OF
SF = OF
SF OF

*JLE
JNA
JNAE
JNB
JNBE

Jump If Less Or Equal

Jump If Not Above
Jump If Not Above Nor Equal
Jump If Not Below
Jump If Not Below nor equal

ZF =1 or SF OF
CF =1 or AF = 1
CF =1
CF =0
CF =0 or ZF = 0

40

Instruction

Description

Jump if ...

JNC
JNE
*JNG
*JNGE
*JNL

Jump If No Carry
Jump If Not Equal
Jump If Not Greater
Jump If Not Greater nor Equal
Jump If Not Less

CF =0
ZF = 0
ZF = 1 or SF OF
SF OF
SF = OF

*JNLE
OF
*JNO
JNP
*JNS
JNZ

Jump If Not Less Nor Equal

ZF = 0 and SF=

Jump If No Overflow
Jump If No Parity (odd)
Jump If No Sign
Jump If Not Zero

OF = 0
PF = 0
SF = 0
ZF = 0

*JO
Jump On Overflow
JP
Jump On Parity (Even)
JPE
Jump If Parity Even
JPO
Jump If Parity Odd
*JS
Jump On Sign
JZ
Jump
Zero
* Pertinent for signed
(2sIfcomplement)
arithmetic.

OF = 1
PF = 1
PF = 1
PF = 0
SF = 1
ZF = 1

41

String instructions
Mnemonic

Assembler format

Flags

OF DF IF TF SF ZF AF PF CF

REPEAT PREFIXES
REP

REP

REPE /

REPE

REPZ
REPNE /

REPNE

*
*

*
*

*
*

*
*

*
*

*
42*

MOVS
REPNZ

MOVS

MOVSB
MOVSW

MOVSB
MOVSW

MOVE
dest-string,sourcestring

COMPARE
CMPS

CMPS

CMPSB
CMPSW

CMPSB
CMPSW

dest-string,sourcestring

Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

SCAN
SCAS
SCASB
*
SCASW
*
LODS
LODSB
LODSW
STOS
STOSB
STOSW

SCAS dest-string
SCASB

*
*

*
*

*
*

*
*

*
*

SCASW

LOAD AND STORE

LODS
source-string
LODSB
LODSW
STOS
dest-string
STOSB
STOSW

Note: - means unchanged and * means changed.

43

Interrupt instructions
Mnemonic
INT

Assembler format
INT

interrupt-type

Flags

OF DF IF TF SF ZF AF PF CF
-

INTO
INTO
- Note:
-means unchanged
IRET
IRET and * means changed.
* *
When INT is executed, the 8088 does the following:

1. Push the flags register onto the stack.

2. Clear the Trap Flag (TF) and the Interrupt Enable / Disable Flag(IF), to disable
single- stepping and lock out other maskable interrupts.
3. Push the CS register onto the stack.
4. Calculate the address of the interrupt vector,by multiplying interrupt-type by 4.
5. Load the second word of the interrupt vector into CS.
6. Push the IP onto the stack.
7. Load the first word of the interrupt vector into IP.
In summary, after INT has executed, the flags, CS and IP are on the stack, TF and IF are 0,
and the CS:IP combination points to the starting address of the interrupt service routine. Now
the 8088 begins executing the interrupt service routine.

44

Processor control instructions

Flags

Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

FLAG OPERATIONS
STC

STC

CLC

CLC

CMC
*
STD

CMC

STD

CLD

CLD

STI
HLT
WAIT
CLI
ESC
LOCK

STI
HLT
WAIT
CLI
ESC
LOCK

- - -- -- - -

--

--

--

EXTERNAL SYNCHRONIZATION

ext-opcode,source

--

--

1 - -0 -- - -

45

Flags
Mnemonic

Assembler format

OF DF IF TF SF ZF AF PF CF

NO OPERATION
NOP

NOP

Note: - means unchanged and * means changed.

NOP is also convenient when you are testing sequences of instructions in your
computer. That is, you can make NOP the last instruction in a test program- a
convenient spot at which to stop a trace. You will probably find other uses for
this innocuous, but handy instruction.

46

DATA TRANSFER INSTRUCTIONS

MOVE (MOV)
Transfer byte or word data between a register and a memory location or
between two registers or an immediate value into a register or memory
location.
Excludes
data movement between two memory locations
immediate value cannot be directly loaded to segment registers (if required
that is to be done through some general purpose register).
CS register cannot be used as destination.

Push ( PUSH) and Pop (POP)

Push deposits a word sized register or memory operand on to the top of the
stack. Conversely, Pop retrieves a word from the top of the stack and puts it
into memory or a register.
Register includes general purpose register, special purpose register also CS.

47

MOV mem/reg , mem/reg

MOV AX,BX
(AX) =(BX) = 3000H

CS =0000
ES =3000
CX =0010

DS =1000 SS =2000
AX =2000 BX =3000
DX =4000 SS =0100

MOV AX, [BX]

(AX) = (13000H) W

BP =0200

SI = 0300
IP = 0100

DI = 0400

MOV [BX+SI+2040],AL
(15340H) B= (AL)
MOV reg,data
MOV mem/reg, data

(this is generally not used to move data to registers)

MOV Acc, Mem

MOV Mem, Acc

(Direct addressing specially for Accumulator)

MOV Seg reg, mem/reg

MOV mem/reg, Seg reg

(except Code Segment Register)

PUSH reg
PUSH mem/reg
PUSH Seg reg
PUSHF (Push flag reg.)
LAHF
SAHF

POP reg
POP mem/reg
POP Seg reg
POPF (Pop to flag reg.)

(Load lower byte of PSW to AH)

(Store the content of AH to lower byte of PSW)

48

Exchange (XCHG)
Exchange the contents of two registers or exchange the contents of a register
and memory location ( Segment registers cannot be used as operands)
XCHG
AX,BX
XCHG
AL,BH
XCHG
WORDLOC,DX
XCHG
DL,BYTELOC

Translate (XLAT)
Looks up a value in a byte table and load it into AL. The table may be 256 byte
long. Before executing XLAT, BX must contain the starting address of SOURCE
TABLE and AL must contain the index into the table.
To get the tenth byte of STABLE
MOV
AL,10
MOV
BX, OFFSET STABLE
XLAT
STABLE
The 8 bit content of AL is added with the 16 bit content of BX. This forms the
effective address for DS register. After execution the content of the
corresponding memory location gets loaded to AL register.

49

In (IN) and Out (OUT)

Accumulator is AL for byte transfers and AX for word transfers. Generally , port
is a decimal value between 0 and 255.
The contents of the DX register may also be specified as the port operand
giving access to 64K different ports.
IN
AL,200
IN
AL,DX
OUT
30,AX
OUT
DX,AX
IN
AL,PORTVAL (Port is named by a constant)

Load Effective Address (LEA)

Transfers the offset address of a memory operand into any 16-bit general
purpose pointer or index register. The memory operand can be subscripted for
lot more addressing flexibility.
LEA SI, [BX+0F62]
(SI) 3F62H

50

Load pointer using DS (LDS)

Fetches a 32-bit doubleword from memory and loads the high-order 16 bits into a
specified word register and the low-order 16 bits into DS.
The specified register may be any general purpose register or index register.
LDS SI, [1625]
(SI) (11625H)W
(DS) (11627H)W
Load Pointer Using ES (LES)
Same as LDS except ES is used instead of DS.
These instructions facilitate switching data segments by simultaneously loading a base
or index register and a segment register.
Load AH From Flags (LAHF)
CF,PF,AF,ZF and SF are copied in respective positions in AH register.
Store AH Into Flags (SAHF)
it performs the reverse operation.
Push Flags Onto Stack (PUSHF) , Pop flags off stack (POPF)
Entire 16 bits of the flag register are transferred to and from the stack. Essentially
51
same as Push and Pop without any operand - flag register is referenced implicitly.

ARITHMETIC INSTRUCTIONS
Add (ADD) , Add With Carry (ADC)
for ADD instruction:
destination = destination + source
for ADC instruction:
destination = destination + source + carry
either bytes or words can be added. The following forms are legal:
Register

= Register

Register = Register

+ Register

+ [Memory]

[Memory]

= [Memory]

+ Register

[Memory]

= [Memory]

+ data

[Register]

= [Register]

+ data

Illegal forms are:

[Memory] = [Memory] + [Memory]
[ data ] = [ data ] + Register / [Memory]

52

ASCII Adjust for Addition (AAA)

Decimal Adjust for Addition (DAA)
Neither instructions takes any operand but both assume that the result to be
adjusted is in the AL register.
AAA instruction convert the contents of AL to an unpacked decimal digit. It
checks the low four bits of AL. If these bits hold a valid BCD digit ( a value
between 0 and 9) AAA clears the high four bits of AL and the flags AF and CF.
However, if the low four bits of AL hold a value greater than 9 or if AF is set to 1,
AAA adjusts the result as follows:
a) Add 6 to the AL register
b) ADD 1 to the AH register
c) Set AF and CF to 1
d) Clear the high four bits of AL .
Similarly DAA instruction converts the contents of AL to two packed decimal
digits. The adjustment procedure is:
a) If the low four bits of AL hold a value greater than 9 or if AF is 1 add 6 to AL
and set AF to 1.
b) Next if the high four bits of AL hold a value greater than 9 or if CF is 1 add 60H
to AL and set CF to 1.
53

Increment Destination by One (INC)

1 is added to a register or memory operand but unlike ADD affects neither the
carry flag nor the zero flag. It is applicable to general purpose registers, or index
registers or pointers but is not applicable to segment register.
Decrement Destination by One (DEC)
The content of the register or memory operand is decremented by one. Neither CF
flag nor ZF is affected.
Negate (NEG)
It forms the 2s complement of the content of the designation and stores into the
destination.
(destination) = 2s complement (destination)
destination may be register or any memory location.
Useful to subtract a register or memory from an immediate value.
NEG

AL

ADD

AL,100

54

Subtract (SUB) and Subtract with borrow (SBB)

For SUB
destination = destination - source
For SBB
destination = destination - source - carry
The above instructions support subtracting one register from another, a memory
operand from a register or vice-versa or an immediate value from a register or a
memory location.
Decimal Adjust for Subtraction (AAS and DAS)
Both instructions assume that the number to be adjusted is in the AL register.
AAS examines the low four bits of AL.. If these bits hold a valid BCD digit (a value
between 0 & 9) AAS clears the high four bits of AL and the AF and CF flags.
However,if the low four bits of AL hold a value greater than 9 or if AF is set to 1
AAS performs the following adjustment.
a) Subtract 6 from AL
b) Subtract 1 from AH
c) Set AF and CF to 1
d) Clear the high four bits of AL.
55

DAS converts the content of AL to two packed decimal digits. The adjustment
procedure is:
a) If the low four bits of AL hold a value greater than 9 or if AF is 1 subtract 6
from AL register and set AF to 1.
b) If the high four bits of AL hold a value greater than 9 or if CF is 1 subtract 60H
from AL register and set CF to 1.
Compare Destination to Source (CMP)
CMP subtracts a source operand from a destination operand and sets or clears
certain flags based on the result but unlike SUB the result is not saved into the
destination.
Unsigned operands
SF
ZF
CF
Source < destination
D
0
0
Source = destination
D
1
0
Source > destination
D
0
1
Signed operands
Source < destination
0
0
D
Source = destination
0
1
D
Source > destination
1
0
D
56

Multiply , Unsigned (MUL)

Integer Multiply, Signed (IMUL)
Source is a byte or word length general register or memory
location. For second operand, MUL and IMUL use the contents of
the accumulator ; AL for byte operations and AX for word operation.
The double length products are returned as follows:
a byte multiplication AH uses (higher byte) and AL (lower byte).
a word multiplication uses DX (higher word) and AX (lower word).
Upon completion of multiplication CF and DF tell how much of the
product is relevant. For MUL if the high order half of the result is
zero both CF & OF are 0 otherwise both are 1 ( same is the case
for IMUL if the high order half is a sign-extension of the low order
half).
Multiplication by an immediate value cannot be done directly. It is to
57
be stored in some register before MUL.

ASCII Adjust for multiplication (AAM)

Convert the product of a preceding byte multiplication into two valid unpacked decimal
numbers. AAM assumes that the double length product is in AX and return the
unpacked decimal numbers in AH and AL (for AAM to work correctly the original
multiplier & multiplicand must have been valid unpacked operands).
Basically AAM divides the content of AL by 10 and stores the quotient and remainder
in AH and AL respectively.
Divide, Unsigned (DIV)
Integer Divide, Signed (IDIV)
Source is a byte or word length divisor in a general register or a memory operand. It
assumes that the dividend is in AH & AL for 8 bit operation and is in DX & AX for 16 bit
operation.
for byte operation the quotient is returned in AL & the remainder is returned in AH
for word operation the quotient is returned in AX & the remainder is returned in DX.
Here the flags are undefined if the result exceeds the capacity of the destination, a
type O interrupt occurs. In DOS environment Divide Overflow message is displayed.
(divide by immediate is not allowed unless it is loaded in some general register).

58

ASCII adjust for division (AAD)

Unlike other adjustments AAD is applied before division
AAD
DIV , BL
AAD converts an unpacked dividend to a binary value in AL.
It multiplies the content of AH by 10 and adds with the
content of AL and puts in AL and zeroes the content of AH.
Sign -Extension Instructions CBW,CWD
CBW reproduces bit 7 of AL throughout AH
CWD reproduces bit 15 of AX throughout DX
59

With the help of these instruction we can have

operation on mixed-size-data.
CBW
ADD AX , BX } add a byte in AL to a word in
BX
CBW
IMUL BX } multiply a byte in AL with a word
in BX
CWD
INDIV BX } divide a word in AX by a word in
BX

60

1)

2)
3)

CONTROL TRANSFER INSTRUCTIONS

Instructions that execute procedures must perform three
functions :
They must include some provision for saving the contents
of the instruction pointer (I P).Once the procedure has
been executed, this address will be used to return to the
proper place in the program.This address is usually called
a return address.
They must cause the microprocessor to begin executing
the procedure.
They must use the stored contents of the IP to return to the
program and continue executing the program at this point.
These functions are performed by a pair of instructions.
61

CALL & RET :

CALL pushes the return address onto the stack and the
size of this return address is either 16 bits long or 32
bits long depending on whether the procedure called is
NEAR or FAR.
For NEAR procedure CALL pushes only the offset in
the IP. For FAR procedure CALL pushes the contents
of CS register and then the offset in IP.
With the return address saved on the stack, CALL loads
the offset address of the procedure into IP. If the
procedure is FAR , CALL also loads the segment value
of the procedure into the CS register.
After completion of the procedure RET undoes
everything that CALL did.
62

So far we have discussed direct CALL. One can also make

indirect calls through memory location on register.
NEAR procedure can be called through a register or a wordsize memory variable.
CALL BX
from BX
CALL WORD PTR [BX] from [DS]x16 + [BX]
CALL WORD PTR [BX] [SI] from [DS]x16+[BX]+VAR
CALL WORD PTR VAR
CALLWORD PTR VAR [BX] from [DS]x16+[BX]+VAR

CALL MEM WORD

CALL WORD PTR ES : [BX][SI] from extra segment
CALL WORD PTR [BP] from stack segment
63

Similarly, FAR procedure may be called indirectly

through a doubleword size memory variable.
CALL DWORD PTR [BX] from Data segment
CALL MEM DWORD
CALL DWORD PTR SS:VAR[SI] from stack
segment
Procedures can be nested and level of nesting is
only limited by the capacity of the stack segment.
Since a stack segment is 64 KB, the nesting
capabilities are virtually unlimited.
64

Unconditional Jump (JUMP)

General format for JMP instruction is JMP target
where target follows the same rules as the call operand
Target can be NEAR or FAR, direct or indirect.
In case of NEAR direct jump if the label lies within
-128 bytes or +127 bytes of the JMP instruction we
can define the jump offset by a single byte by declaring
SHORT jump.
JMP SHORT NEAR LABLE is a two byte instruction
and does the same in same time as JMP NEAR LABEL
but takes one byte less memory
(If NEAR or FAR is not mentioned assembler by default
considers it as NEAR.
65

Conditional Jump
Here the assembler recognizes some of these
instructions by two or three different mnemonics,
basically they are provided for convenience and
better readability.
Most important thing to be noted is that
conditional jump takes only short-label i.e. the
jump must be no more than -128 bytes or +127
bytes away from the conditional transfer
instruction.

66

Iteration Control Instructions

Basically conditional transfers,but have a very special
use CX is used as a Count Register and each execution
of the iteration control instruction decrement CX by 1.
LOOP
LOOP , 8 bit displacement
Decrements CX by 1 and transfers control to a short label
target if CX is no zero.
MOV
CX,100
START : _______
_______
LOOP START

67

Many applications involve loops that should terminate

if something happens within the loop before CX
reaches zero.
LOOPE/LOOPZ
LOOPE, 8 bit displacement
decrements CX by 1, then jumps if CX< >0 and ZF=1
LOOPNE/LOOPNZ LOOPNE, 8 bit displacement
decrements CX by 1, then jumps if CX< >0 and ZF=0

68

Shift & Rotate Instructions

Shift arithmetic left SAL
Shift arithmetic right SAR
Both are used for shifting signed nos. SAR preserves the
sign of the operand by replicating the sign bit throughout
the shift operation.
SAL does not preserve the sign bit, but puts 1 in the
overflow flag if the sign ever changes.
Shift logical left SHL
Shift logical right SHR
Both are used for shifting unsigned nos. In both cases the
vacated bit is filled by 0.
69

(In the case of SAL the right most vacated bit

receives 0 after shift and in the case of SAR the
sign bit gets extended in the vacated bit position)
All shift and rotate instructions take two
operands :
A destination and a count. The destination may
be a general register or a memory location of
either byte or word length. The count may be 1
or an unsigned value in CL.
70

Multiplication / Division using shift instructions

MOV CL , 2
SHL AX , CL
SAL AX , CL
SHR AX , CL
SAR AX , CL

Multiply an unsigned no. by 4

Multiply a signed no. by 4
Divide a unsigned no. by 4
Divide a signed no. by 4

Multiplication of the contents of AX by 10

(considering the result within 16 bits and AX be the
destination ).
MOV BX , AX
MOV CL , 2
SHL AX , CL
ADD AX , BX
SHL AX , 1

even though it involves 5

instructions the sequence is
3 times faster than a single
MUL instruction (113 cycles).

71

Rotate Left ROL

Rotate Right ROR
The bit displaced out of one end of the
operand enters the opposite end and also gets
copied in CF.
Rotate Left through carry RCL
Rotate Right through carry RCR
Total shifting operation takes place
considering the carry bit alongwith the
operand.

72

73

Interrupt (INT)
INT interrupt type
( INT xx )
where interrupt type is anything between 0 to 255
(i.e. ,altogether 256 interrupt types)

When INT is executed the following things happen.

1.Push the flags register onto the stack.
2.Clear the trap flag (TF) and the interrupt enable/disable flag
(IF) to disable
single- stepping and lock out other maskable interrupts.
3.Push the CS register onto the stack.
4.Calculate the address of the interrupt vector by multiplying
interrupt type by 4.
5.Load the second word of the vector interrupt vector into CS.
6.Push the IP onto the stack.
7.Load the first word of the interrupt vector into IP.
74

The 256 interrupt vectors are located in the

lowest locations in memory.Since each is four
bytes long, they occupy a total of 1K bytesabsolute addresses 0 through 3FFH.
Out of 256 interrupts types Intel has decreed
the first five, must be allocated to internal
interrupts in every 8086/8088 system.
Type 0,Divide by zero
Type 1,Single step
Type 2,Non markable interrupt
Type 3,Breakpoint
Type 4,Overflow.
75

Type 5 through type IFH perform dedicated functions

for the computers basic I/O (system BIOS).
Further DOS reserves interrupt types 20H through
3FH.
Interrupt if overflow (INTO)
The interrupt if overflow (INTO) is a conditional
interrupt instructions. It initiates an interrupt if the
overflow flag is set (1) and it activates a type 4
interrupt.
Interrupt Return (IRET)
Interrupt service routine is just alike normal
procedure routines but the last instruction of ISR will
be IRET instead of RET.
IRET pops three 16 bit values of the stack and loads
then into IP,CS and Flag register respectively (Here
PSW register content is poped in addition to what
RET does,as interrupt call automatically pushes
76
PSW.

Processor Control Instructions Flag Operations

STC Set carry bit CF
CLC Clear carry bit CF
CMC Complement carry bit CF
STD Set direction flag bit DF
CLD Clear direction flag bit DF
STI Set interrupt flag IF, which lets the 8088 respond to maskable interrupts from
external devices.
CLI Set interrupt flag IF, which lets the 8088 ignore maskable interrupts from
external devices in the system.However the nonmaskable interrupts can be
processed.
No Operation (NOP)
It performs no operation,it affects no flags,no registers and no memory locations.It
does nothing other than advance the Instruction Pointer (IP).
Halt (HLT)
Put 8088 into a halt state.In this state processor sits idle and executes no
instructions.It leaves the halt state if one resets it or receives an external interrupt
either non- maskable on (if IF =1) maskable.
One uses HLT to make the processor wait for an interrupt before proceeding.

77

Wait (WAIT)
Also puts 8088 into an idle state, but instead of just sitting it checks an
input line called TEST at five clock intervals. If TEST is found low
8088 resumes execution at the instruction following WAIT
otherwise continues to be in idle state. 8088 services interrupts
while idle but upon return from the interrupt it again enters the
WAIT state..

Lock the bus (LOCK)

It is a one byte prefix that may precede any instruction. LOCK makes
the 8088 activate its bus lock signal for as long as the LOCKed
instruction takes to execute. While the LOCK signal is active, no
other processors in the system can use the bus.(This is used in
multiprocessor environment to implement Semaphore.)

ESCAPE (ESC)
Through ESC code other processors in the system receive their
instructions and operand. Basically 8088 reads the instruction and
operand for the co-processor and then both executes parallely till
synchronization is required.
78

LOCK
This one byte prefix instruction forces (maximum mode) LOCK pin to
go low and this signal in conjunction with the bus arbiter will not allow
the bus transfer until the prefixed instruction is carried out. (It should be
noted that in the case of two consecutive LOCK prefixed instructions,
there will be an unlocked period between these instructions).
If LOCK prefix is used in minimum mode, delays the generation of
HLDA response to a HOLD request until the execution of the locked
instruction is completed.
In multiprocessing environment, for accessing common resources
semaphore is used, which can be implemented by LOCK prefixed
XCHG instruction (SWAP structure) as follows (see next slide).

79

LOCK
Enter
MOV AL, 1
Test semaphore and set busy
BUSY (1)

Semaphore

XX: LOCK XCHG AL,

SEMAPHORE
TEST AL, AL
JNZ XX

AVAILABLE (0)

Use Resource

Set semaphore available

MOV SEMAPHORE, 0

Exit

80

ESC
It performs no operation as far as 8086/8088 is concerned, but provides
another processor (co-processor 8087) an instruction and/or a memory
operand from its program. When used in conjunction with WAIT and
TEST, ESC can initiate a subroutine that executes concurrently in
another processor.
Processor B

Begin

End

ESC - Test = 1
Processor
A

Escape

Continue till
result of B
is required

Test = 0

Wait

Continue

81

MOVE STRING (MOVS)

MOVS dest-string , source-string
Copies one byte/word from source string in data segment pointed by SI to the destination
string in extra segment pointed by DI.
The segment assignment for SI can be overridden but not for DI.
Every multi-element MOVS operation involves five steps.
1> Clear DF (CLD) or set DF (STD), depending on whether you want the move to progress
toward higher addresses in memory or lower addresses in memory respectively.
2> Load the offset of the source string into SI.
3> Load the offset of the destination string into DI.
4> Load the element count in CX.
5> Execute MOVS instruction with REP prefix.
CLD
LEA SI, SOURCE
LEA DI, ES : DEST moves 100 bytes from
MOV CX, 100
source string in data segment
REP MOVS DEST,SOURCE to destination string in extra segment.
(If we make the ES have the same value as the DS, 8088 innocently copies the source string
in the data segment with an idea of extra segment).
MOVSB move byte string
MOVSW move word string
Dont need any operand; basically supported by the microprocessor.

82

STRING INSTRUCTIONS
Repeat prefixes causes a string instruction to be executed the number of times
specified in the CX register.
MOV CX , 500
REP MOVS Dest , Source
Source is the string in the segment pointed by SI
Destination is the string in the extra segment pointed by DI.
If DF=0 SI & DI gets incremented after each
execution of string instruction.
DF=1 SI & DI gets decremented after each
execution.
REPE
REPEAT if equal
Causes the instruction to be repeated as long as ZF = 1 and CX != 0.
MOV CX , 100
REPE CMPS Dest , Source
Continues comparison for 100 elements or till a mismatch occurs.
REPE
REPEAT if not equal
Causes the instruction to be repeated as long as ZF = 0 and CX != 0.

83

Compare String Instructions

Compare String (CMPS)
Compares the elements of a source string in data segment
addressed by SI with the elements of a destination string in extra
segment addressed by DI with the no. of elements to be compared
in CX.
Like CMP instruction,CMPS compares the two operands by
subtracting them. However, CMP subtracts the source operand
from the destination operand, but CMPS subtracts the destination
operand from the source operand. This means the conditional
transfer instructions that follow a CMPS instruction must be
different from that follow a CMP instruction.
Here it may be noted that repeat prefix REP has no meaning with
CMPS as it would only return the flags result of comparing the
two final elements. With CMPS the repeat prefixes that may be
used are REPE or REPNE.
84

Checking Results
Since repeated compare operations can terminate on either two
conditions.
Contents of CX are zero
ZF changed to 0 (REPE)/to 1 (REPNE)
One may want to determine which of these caused the termination.
Easiest way to do this is using JZ on JNZ instruction following CMPS.
CLD
MOV CX,100
REPNE:CMPS dest, source :Search for a match
JNZ Not found
:Matching elements found?
:Yes, continue here
Not found:No,continue here
Compare Byte String CMPSB | dont need any operand, DI
Compare Word String CMPSW |&SI with ES &DS are used.

85

Scan String Instructions

Scan String (SCAS)
SCAS Dest String
Let us search a string in the extra-segment for a specified value in AL for byte
string and in AX for word string. The offset of the strings first element is in
DI.
This is similar to compare with accumulator operation affecting the flags in the
same way as the string compare instructions.
To operate on more than one string element,repeat prefix REPE or REPNE may
be used.
CLD
LEA DI, ES:B-string
MOV AL, 10
Scans upto 100 byte elements
MOV CX, 100
of the byte string B-string to
REPE SCAS B-String
locate the first elements that
JCXZ There
does not contain 10.If found
continues otherwise jumps to
There:to there.
Compare Byte String SCASB |doesnt require any operand
Compare Word String SCASW | DI & ES in in default used.

86

Load String and Store String Instructions

Once an element is located , in a desired string with CMPS and SCAS
Instructions, one may want to perform some operation on that element.
One may want to read the element into a register for subsequent
processing or change the element in memory.

Load String (LODS)

Transfer a source-string operand in data segment addressed by SI to
accumulator AL ( Byte operation) or AX ( Word operation).
CLD
LEA DI, ES; DEST
LEA SI, Source
MOV CX, 500
REPE CMPSB
Search for a mismatch
JCXZ Match
Mismatch found ?
DEC SI
Yes, adjust SI
LODS Source
Read element into AL and
----process it
Match : ----No, continue from here

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Store String ( STOS )

Transfer an operand from accumulator AL ( byte operation )
or AX (word operation) to the destination string operand in
the extra segment, addressed by DI, then adjust DI to point
to the next element. If DF is 0, DI is incremented, if DF is
1, DI is decremented.
CLD
LEA DI , ES : WString
MOV AX , 0
Scans 200 elements word
MOV CX , 200
strings Wstrings for the
REPNE SCASW
first non-zero element.
JCXZ ALLO
If such an element is found,
SUB DI , 2
this word and next five words
MOV CX , 6
are filled with 0.
REP
STOS Wstring
ALGO : -------

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THANKS
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