ELEN 468

Advanced Logic Design

Lecture 17
MIPS Microprocessor

Computer Architecture
CISC

Complex Instruction Set Computer

Intels x86, Motorolas 680x0

RISC

Reduced Instruction Set Computer

MIPS
Microcomputer without Interlocked Pipeline

Stages
Millions of Instructions Per Second
Strongly pipelined architecture
DECs Alpha, HPs Precision

Registers
32 32-bit (word) registers

$a0 - $a3: argument registers

$v0 - $v1: return values
$ra: return address register
$sp: stack pointer
$fp: frame pointer
$gp: global pointer
$zero: always equals 0
$s0 - $s7: preserved on a procedural call
$t0 - $t9: not preserved by callee on a procedural
call

Preservation by callee: values are not changed by

a system/function call.
3

Arithmetic Operations
add a, b, c # a = b + c
add $t0, $s1, $s2
sub a, b, c # a = b c
sub $s0, $t0, $t1
Arithmetic operations occur only on
registers

Data Transfer
lw $t0, 8($s3) # load $t0 with data from memory
# base address in $s3, offset 8
sw $t0, 48($s3) # store word

12

101

110

10

1001

Addres
s

Memory

Byte 8 bits
Word 32 bits
Memory in words
Address to byte
level
5

MIPS Fields
Rtype
I-type

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

op

rs

rt

op: basic operation, also called opcode

rs: the first register source operand
rt:

addres
s

R-type: the second register source operand

I-type: destination register

rd: the register destination operand

shamt: shift amount in shift instructions
funct: selects the specific variant of the operation in op field,
also called function code
address: offset of memory address in data transfer instructions
6

Examples of Machine Code

op

rs

rt

rd
17

sham
t
0

func
t
32

18

19

18

19

17

34

op

rs

rt

35

18

17

100

lw $s1, 100($s2)

43

18

17

100

sw $s1,
100($s2)

add $s1, $s2,

$s3
sub $s1, $s2,
$s3

address

Some Other Instructions

beq $s3, $s4, L1
bne $s3, $s4, L1
j L1
jr $t0
slt $t0, $s1, $s2
sll $t2, $s0, 8
srl $t2, $s0, 8
addi $sp, $sp, 4
nop

#
#
#
#
#

go to branch L1, if equal

go to branch L1, if not equal
jump to branch L1
jump based on $t0
set value of $t0 to 1, if less than
# reg $t2 = reg $s0 << 8 bits
# reg $t2 = reg $s0 >> 8 bits
# $sp = $sp + 4
# do nothing

MIPS Addressing Mode

Register addressing: the operand is a
register
Base or displacement addressing: the
operand is at the memory whose address
is the sum of a register and a constant
Immediate addressing: the operand is a
constant
PC (Program Counter)-relative addressing:
address is the sum of PC and a constant in
the instruction
9

Steps for MIPS Instructions

1. Fetch instruction from memory
2. Read registers while decoding the
instruction
3. Execute the operation or
calculate an address
4. Access an operand in data
memory (for lw and sw)
5. Write the result into a register

10

Implement Instruction
Fetch
Add

4
P
C

Read
addres
s

Instructio
n
Instruction
memory

11

Datapath for R-type

Instructions
5

5
Instructio
n

Read
register
Read
1
data 1
Read
register
2
Registers
Write
register
Write
data

Read
data 2

32

Contro
l

ALU
Result 32
32

Reg_writ
e
12

Example of Instruction Execution

Time
Instructio
n

Instructio Registe
ALU
n fetch
r read operatio
n

Memor
y
access

lw

sw

R-format
(add, sub)

Branch

Registe Total
r write time
1

8
7

6
5

13

Unpipelined vs. Pipelined

2
lw $t1, 8($s1)
lw $t2, 16($s2)
lw $t3, 12($s3)

lw $t1, 8($s1)
lw $t2,
16($s2)
lw $t3,
12($s3)

IF

ID ALU

1
0

1
2

1
4

1
6

1
8

MEM WB

IF: Instruction fetch

IF ID ALU MEM WB
ID: Instruction
decode and read
MEM: Memory
IF
register
access
ALU: Execution or
WB: Write back to
address
reg
IF calculation
ID ALU MEM WB
IF

ID ALU
IF

MEM WB

ID ALU

MEM WB
14

Instruction Sets for

Pipelining
All instructions have the same
length
There are only a few instruction
formats
Memory operands only appear in
loads or stores
Operands must be aligned in
memory
15

Pipeline Hazards
Situations when the next
instruction cannot execute in the
following clock cycle

Structural hazards
Control hazards
Data hazards

16

Structural Hazards
Hardware cannot support the
combined instructions that we want
to execute in the same clock cycle
Example: if there is only one
memory, then memory access and
instruction fetch cannot be
executed simultaneously
Solution: add hardware
17

Control Hazards
Decision-making depends on the result of
an instruction that has not been finished
Example: PC following a branch
instruction depends if branch is taken or
not
Solutions

Predict: execute next instruction anyway, if

branch is taken, retract the decision
Dynamic prediction based on smart guess
18

Data Hazards
An instruction cannot be executed until a
data is available from another instruction
Example: add $s0, $t1, $t2
sub $t2, $s0, $t3
Solution:

Bypassing: result can be fed to next

instruction execution without loading to a
register
19