Interrupt Interface of the 8088 and

8086 Microcomputer

11.1 Interrupt Mechanism, Type, and

Priority
Interrupts provide a mechanism for quickly
changing program environment.
Transfer of program control is initiated by
the occurrence of either an event internal to
the microprocessor or an event in its
external hardware.

11.1 Interrupt Mechanism, Type, and

Priority
When an interrupt signal occurs in external hardware
indicating that an external device, such as a printer,
requires service, the MPU must suspend what it is
doing in the main part of the program and pass control
to a special routine (interrupt-service routine) that
performs the function required by the device. In the
case of our example of a printer, the routine is usually
called the printer driver, which is the piece of
software when executed drives the printer output
interface.

Interrupt mechanism
The 8088 and 8086 microcomputers are
capable of implementing any combination
of up to 256 interrupts.
As Fig. 11-2, they are divided into five
groups: external hardware interrupts,
nonmaskable interrupt, software interrupts,
internal interrupts, and reset.

Figure 11.2 Types of interrupts and their

priority

11.2 Interrupt vector table

An interrupt vector table is used to link the interrupt
type numbers to the location of their service routine
in the program-storage memory.
Fig. 11-2 contains 256 address pointers (vectors),
which are identified as vector 0 through vector 255.
That is, one pointer corresponds to each of the
interrupt types 0 through 255. These pointers
identify the starting location of their service routines
in program memory. The contents of this table may
be either held as firmware in EPROMs or loaded
into RAM as part of the system initialization routine.

11.2 Interrupt vector table

Fig. 11-3 starts at address 0000016 and end at
003FE16. This represent the first 1Kbytes of
memory.
Each of the 256 pointers requires two words (4
bytes) of memory and is always stored at an evenaddress boundary. The higher-addressed word of
the two-word vector is called the base address. IT
identifies the program memory segment in which
the service routine resides.

Figure
11.3

11.3 Interrupt Instructions

Figure 11.4

8088/86 Hardware Interrupts pins

INTR: Interrupt Request.
Input signal into the CPU
If it is activated, the CPU will finish the current instruction and
respond with the interrupt acknowledge operation
Can be masked (ignored) thru instructions CLI and STI

NMI: NonMaskable interrupt.

Input signal
Cannot be masked or unmasked thru CLI and STI
Examples of use: power frailer. Memory error

INTA: Interrupt Acknowledge.

Output signal

11.External
HardwareInterrupt
Interface
Signal
Figure 11.5

Figure 11.6

Figure 11.7

Figure 11.10

Figure 11.12

8259
8259 is Programmable Interrupt Controller (PIC)
It is a tool for managing the interrupt requests.

8259 is a very flexible peripheral controller chip:

PIC can deal with up to 64 interrupt inputs
interrupts can be masked
various priority schemes can also programmed.

originally (in PC XT) it is available as a separate IC

Later the functionality of (two PICs) is in the
motherboards chipset.
In some of the modern processors, the functionality of the
PIC is built in.

Pin description

8-bit bi-directional data bus, one address line is needed,

PIC has two control registers to be programmed, you can think of them as two
output ports or two memory location.

The direction of data flow is controlled by RD and WR.

CS is as usual connected to the output of the address decoder.
Interrupt requests are output on INT which is connected to
the INTR of the processor. Int. acknowledgment is received
by INTA.
IR0-IR7 allow 8 separate interrupt requests to be inputted to
the PIC.
sp/en=1 for master , sp/en=0 for slave.
CAS0-3 inputs/outputs are used when more than one PIC to
cascaded.

Figure
11.13

Figure
11.14

Figure
11.15

Ex 11.3

Ex 11.4

Ex 11.5

Ex 11.6

Figure
11.16

Ex 11. 7

Figure 11.17

Ex 11.8

Figure 11.18

Figure 11.18

Figure 11.18

Ex 11.9

Figure 11.19

Figure
11.20

Ex
11.9

Ex 11.9

Figure
11.21

Figure
11.22

Figure 11.23

Figure 11.24