Sequential Logic
SEQUENTIAL LOGIC
Memory Elements
Latches: S-R Latch, D Latch
Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops
Asynchronous Inputs
Finite State Machines
Memory
Memory Unit
Read/Write Operations
Memory Arrays
2011 Sem 1
Sequential Logic
INTRODUCTION (1/2)
Combinational Circuit
Sequential Circuit
Each output depends on both
present inputs and state.
Combinational
Logic
::
outputs
inputs : :
Combinational
Logic
::
outputs
Memory
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Sequential Logic
INTRODUCTION (2/2)
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Sequential Logic
command
stored value
Characteristic table:
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Command
(at time t)
Q(t)
Q(t+1)
Set
Reset
Memorise /
No Change
0
1
0
1
Sequential Logic
command
clock
Positive edges
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stored value
Negative edges
Sequential Logic
command
clock
Positive edges
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stored value
Negative edges
Sequential Logic
Pulse-triggered
Latches
ON = 1, OFF = 0
Positive pulses
Positive edges
Negative edges
Edge-triggered
Flip-flops
Positive edge-triggered (ON = from 0 to 1; OFF = other time)
Negative edge-triggered (ON = from 1 to 0; OFF = other time)
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Sequential Logic
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Sequential Logic
ELEMENTS OF A FSM
A finite
set of states
set of inputs
A finite set of outputs
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Sequential Logic
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EXAMPLE
Final State
Input
Retire
State
Leave == 0
Death
Graduate
er
ov
Age == 6
n
tio
ca
Va
Ag
e
re
Bo
==
65
Start State
Heart attack
Bored
Born
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Education
Work
Sequential Logic
Play
State Transition
11
Release / C
Press / A
A:
X = current_mouse_position();
B:
X = current_mouse_position();
Draw line from X to Y;
C:
The traffic light should change from one direction to the other only if
a car is waiting to go in the other direction; otherwise, the light
should continue to show green in the same direction as the last car
that crossed the intersection.
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Sequential Logic
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STATE DIAGRAM
Two states:
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Sequential Logic
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Memory elements
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Sequential Logic
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For active-high input S-R latch (also known as NOR gate latch)
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Sequential Logic
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Q 11000
10001 S
Q' 0 0 1 1 0
S
1
0
0
0
1
R
0
0
1
0
1
Q Q'
1 0
initial
1 0 (afer S=1, R=0)
0 1
0 1 (after S=0, R=1)
0 0
invalid!
Block diagram:
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Q'
Sequential Logic
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Q'
NC
NC
1
0
1
0
1
1
1
0
0
0
1
0
S R
0
0
1
1
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0
1
0
1
No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.
Q'
Q(t+1)
No change
Q(t)
0
Reset
1
Set
indeterminate
Sequential Logic
Q(t+1) = S + R' Q
S R = 0
18
EN
EN
Q'
Q'
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Sequential Logic
19
EN
EN
Q'
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Sequential Logic
Q'
20
When EN is high,
D = HIGH latch is SET
D = LOW latch is RESET
Characteristic table:
Sequential Logic
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FLIP-FLOPS (1/2)
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Negative edges
Sequential Logic
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FLIP-FLOPS (2/2)
C
R
C
Q'
C
Q'
Q'
C
R
C
Q'
C
Q'
Q'
Sequential Logic
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S-R FLIP-FLOP
C
R
Q'
CLK
Q(t+1)
Comments
0
0
1
1
0
1
0
1
Q(t)
0
1
?
No change
Reset
Set
Invalid
Sequential Logic
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S-R FLIP-FLOP
CLK
SET
RESET
Q
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Sequential Logic
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D FLIP-FLOP
CLK
Q(t+1)
Q'
1
0
1
0
C
R
Comments
Set
Reset
Sequential Logic
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D FLIP-FLOP
CLK
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Sequential Logic
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D FLIP-FLOP vs D LATCH
CLK for FF
Connect to EN for latch
D
Q for
D-flip-flop
Enabled!
Q for
D-latch
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Sequential Logic
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D FLIP-FLOP
CLK
X
Combinational
logic circuit
CLK
D
Transfer
CLK
Q1 = X*
Q'
Q
Q2 = Y*
Q'
Q
Q3 = Z*
Q'
Sequential Logic
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No invalid state.
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Sequential Logic
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Pulse
transition
detector
CLK
Q'
Characteristic table:
J
CLK
Q(t+1)
Comments
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)'
No change
Reset
Set
Toggle
Sequential Logic
J K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
1
1
0
1
0
31
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Sequential Logic
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Sequential Logic
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T FLIP-FLOP
CLK
CLK
Q'
Q'
Characteristic table:
T
CLK
Q(t+1)
Comments
0
1
Q(t)
Q(t)'
No change
Toggle
Q T
0
0
1
1
0
1
0
1
Q(t+1)
0
1
1
0
Sequential Logic
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Frequency Divider
CLK
Frequency = f
CLK
Q
Frequency = f / 2
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Sequential Logic
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Frequency Divider
What
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Sequential Logic
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A 4 bit counter
A BCD
CLK
CLK is at frequency f: 1010101010101010101010101010101010
D is at frequency f/2: 110011001100110011001100110011001111
C is at frequency f/4: 111100001111000011110000111100001111
B is at frequency f/8: 1111111100000000111111110000000011111111
A is at frequency f/16: 11111111111111110000000000000000
Recall our truth table! Count down
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Sequential Logic
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Sequential Logic
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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Sequential Logic
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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Sequential Logic
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
40
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Sequential Logic
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
41
Decimal counter
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Sequential Logic
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000
0001
0010
0011
0100
0111
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CLK
Frequency = f
CLK
Frequency = f / 3
A
B
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Sequential Logic
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Synchronous
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counters
Sequential Logic
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Next State
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Sequential Logic
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Sequential Logic
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Present State
Next State
J K
0 0
0 0
0KB1
0 1
X
1 0
1 X0
1 01
1 1
0
1
0
1
0
1
0
1
Q(t+1)
JA
KA
JB
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Sequential Logic
JC
0
0
1
1
1
0
1
0
1
X
1
X
KC
X
1
X
1
48
Step 3: K-map
A
BC
00 01 11
10
BC
00 01 11
10
JA = BC
BC
KA = BC
00 01 11
10
00 01 11
10
JB = C
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BC
KB = C
Sequential Logic
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BC
00 01 11
10
BC
10
JC = 1
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00 01 11
KC = 1
Sequential Logic
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Sequential Logic
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Q T
Next State
TA
TB
TC
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Sequential Logic
0
0
1
1
0
1
0
1
Q(t+1)
0
1
1
0
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BC
00 01 11
10
BC
00 01 11
10
TB = C
TA = BC
A
BC
00 01 11
10
TC = 1
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Sequential Logic
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CLK
CLK
CLK
CLK
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Sequential Logic
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Most
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Sequential Logic
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Sequential Logic
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Input
Next
State
JA
KA
JB
KB
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Sequential Logic
J K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
1
1
0
1
0
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Step 3: K-map
A
BX
00 01 11
10
BX
00 01 11
JA = B
BX
KA = BX
00 01 11
10
BX
00 01 11
10
JB = X
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10
KB = AX + AX
=A X
Sequential Logic
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IMPLEMENTATION OF FSM
CLK
CLK
K
CLK
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Sequential Logic
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Sequential Logic
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PRE
J
CLK
Q'
Q
Pulse
transition
detector
Q'
CLR
CLR
CLK
PRE
CLR
J = K = HIGH
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Preset
Sequential Logic
Toggle
Clear
61
METASTABILITY (1/3)
In reality, nothing is instantaneous. Critical timing parameters must be observed.
CLOCK
tco
DATA
ts setup time
th hold time
tco clock to output time
(propagation delay)
OUTPUT
ts
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th
Sequential Logic
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METASTABILITY (2/3)
If setup and hold times are violated, flip-flop may
oscillate in an indeterminate state between 0
and 1
This is called metastability
Introduces error in the circuits operation
Cannot be absolutely avoided in practice
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Sequential Logic
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METASTABILITY (3/3)
Input
Output
CLK
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Sequential Logic
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TRI-STATE MULTIPLEXERS
A tri-state buffer:
When enabled, connects input to
output
When disabled disconnects input
from output by entering a highimpedance state
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Sequential Logic
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Definitions:
1 byte = 8 bits
1 word: in multiple of bytes, a unit of transfer between main
memory and registers, usually size of register.
1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes;
1 GB (giga-bytes) = 230 bytes; 1 TB (tera-bytes) = 240 bytes.
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Sequential Logic
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Memory hierarchy
Fast, expensive
(small numbers),
volatile
registers
main memory
disk storage
magnetic tapes
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Sequential Logic
Slow, cheap
(large numbers),
non-volatile
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Sequential Logic
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WR
Write data
CLK
CLK
CLK
CLK
Register
Number
4-bit register
Decoder
Read data
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Sequential Logic
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MEMORY (1/2)
Data transfer
Processor
Up to 2k
addressable
locations.
Address
MAR
Memory
0
1
2
3
4
5
MDR
Control lines
(R/W, etc.)
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Sequential Logic
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MEMORY (2/2)
A memory unit stores binary information in groups of bits
called words.
Sequential Logic
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MEMORY UNIT
k address lines
Memory unit
2k words
n bits per word
Read/Write
n
n data
output lines
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Sequential Logic
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READ/WRITE OPERATIONS
Write operation:
Transfers the address of the desired word to the address lines.
Transfers the data bits (the word) to be stored in memory to the
data input lines.
Activates the Write control line (set Read/Write to 0).
Read operation:
Transfers the address of the desired word to the address lines.
Activates the Read control line (set Read/Write to 1).
Memory Enable Read/Write
Memory Operation
0
X
None
1
0
Write to selected word
1
1
Read from selected word
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Sequential Logic
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MEMORY CELL
A single memory cell of the static RAM has the following logic and
block diagrams:
Select
Select
R
Input
Output
BC
Output
Read/Write
Read/Write
Logic diagram
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Input
Block diagram
Sequential Logic
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Logic construction
of a 43 RAM (with
decoder and OR
gates):
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Sequential Logic
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DATA (8)
ADRS (10)
CS
RW
(8)
Output data
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Sequential Logic
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Lines
09
Input data
8 lines
DATA (8)
(8)
ADRS (10)
CS
1K x 8
RW
2x4
decoder
S0
S1
0
1
2
3
1024 2047
DATA (8)
(8)
ADRS (10)
CS
1K x 8
RW
2048 3071
Read/write
01023
DATA (8)
(8)
ADRS (10)
CS
1K x 8
RW
4K 8 RAM.
3072 4095
DATA (8)
(8)
ADRS (10)
CS
1K x 8
RW
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Sequential Logic
Output
data
77
21bit
addresses
19bitinternalchipaddress
A19
A20
2bit
decoder
512K x 8
memory chip
19-bit
address
512kX8
memorychip
8-bit data
input/output
Chip select
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D3124
D2316
D 158
D70
2M 32 memory module
Using 512K 8 memory chips.
Sequential Logic
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END
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Sequential Logic
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