EMBEDDED SYSTEMS

8051 MICROCONTROLLER

Introduction

General-purpose microprocessor

CPU for Computers

No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0
CPU
GeneralPurpose
Microprocessor

Many chips on mothers board

Data Bus

RAM

ROM

I/O
Port

Address Bus
General-Purpose Microprocessor System

Timer

Serial
COM
Port

Microcontroller :

A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU
I/O
Port

RAM ROM
Serial
Timer COM
Port

A single chip
Microcontroller

Microprocessor vs. Microcontroller

Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose

Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
for applications in which cost,
power and space are critical
single-purpose

Three criteria in Choosing a Microcontroller

1.

2.

3.

meeting the computing needs of the task efficiently and cost

effectively

speed, the amount of ROM and RAM, the number of I/O

ports and timers, size, packaging, power consumption

easy to upgrade

cost per unit

availability of software development tools

assemblers, debuggers, C compilers, emulator, simulator,

technical support
wide availability and reliable sources of the microcontrollers.

Block Diagram
External interrupts
Interrupt
Control

On-chip
ROM for
program
code

Timer/Counter

On-chip
RAM

Timer 1
Timer 0

CPU

OSC

Bus
Control

4 I/O Ports

P0 P1 P2 P3

Address/Data

Serial
Port

TxD RxD

Counter
Inputs

Comparison of the 8051 Family Members

Feature
ROM (program space in bytes)
RAM (bytes)
Timers
I/O pins
Serial port
Interrupt sources

8051
4K
128
2
32
1
6

8052
8031
8K
0K
256
128
3
2
32
32
1
1
8
6

Pin Description of the 8051

PDIP/Cerdip
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0
P
) 0.1(AD1)
P0.2(AD2
P
) 0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
P
) 2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

Pins of 8051 2/4

RST pin 9 reset

It is an input pin and is active high normally low .
The high pulse must be high at least 2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the microcontroller
will reset and all values in registers will be lost.
Reset values of some 8051 registers
Way 1 Power-on reset circuit
Way 2 Power-on reset with debounce

Pins of 8051 3/4

/EA pin 31 external access

There is no on-chip ROM in 8031 and 8032 .
The /EA pin is connected to GND to indicate the code is
stored externally.
/PSEN ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
/ means active low.
/PSEN pin 29 program store enable
This is an output pin and is connected to the OE pin of the
ROM.

Pins of 8051 4/4

ALE pin 30 address latch enable

It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and
data by connecting to the G pin of the 74LS373 latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.

Figure 4-2 (a). XTAL Connection to 8051

Using a quartz crystal oscillator

We can C2
observe the frequency on the XTAL2 pin.
XTAL2
30pF
C1
XTAL1
30pF
GND

Figure 4-2 (b). XTAL Connection to an External Clock

Source
N
C

EXTERNAL
Using a TTL oscillator OSCILLATOR
XTAL2 is unconnected.SIGNAL

XTAL2

XTAL1

GND

Example :
Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 s

RESET Value of Some 8051 Registers:

Register
PC
ACC
B
PSW
SP
DPTR
RAM are all zero.

Reset Value
0000
0000
0000
0000
0007
0000

Power-On RESET with Debounce

Vcc

31
10 uF

30 pF

EA/VPP
X1

X2
RST

8.2 K

Pins of I/O Port

The 8051 has four I/O ports

Port 0 pins 32-39 P0 P0.0 P0.7
Port 1 pins 1-8
P1 P1.0 P1.7
Port 2 pins 21-28 P2 P2.0 P2.7
Port 3 pins 10-17 P3 P3.0 P3.7
Each port has 8 pins.

Named P0.X X=0,1,...,7 , P1.X, P2.X, P3.X

Ex P0.0 is the bit 0 LSB of P0

Ex P0.7 is the bit 7 MSB of P0

These 8 bits form a byte.

Each port can be used as input or output (bi-direction).

Registers
A
B
R0

DPTR

DPH

DPL

R1
R2

PC

PC

R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051

Some 8051 16-bit Register

Some Simple Instructions

MOV dest,source
MOV
MOV
MOV
MOV

A,#72H
A, #r
R4,#62H
B,0F9H

MOV
MOV
MOV

DPTR,#7634H
DPL,#34H
DPH,#76H

MOV

P1,A

; dest = source
;A=72H
;A=r OR 72H
;R4=62H
;B=the content of F9th byte of RAM

;mov A to port 1

Note 1:
MOV
A,#72H
After instruction MOV

MOV
A,72H
A,72H the content of 72th byte of RAM will replace in Accumulator.

8086
MOV
MOV
MOV
MOV

8051
AL,72H
AL,r
BX,72H
AL,[BX]

MOV
MOV

A,#72H
A,#r

MOV

A,72H

MOV

A,3

Note 2:
MOV

A,R3

ADD A, Source

;A=A+SOURCE

ADD

A,#6

;A=A+6

ADD

A,R6

;A=A+R6

ADD

A,6

;A=A+[6] or A=A+R6

ADD

A,0F3H

;A=A+[0F3H]

SETB
CLR
SETB
SETB
SETB
SETB
SETB

bit
bit
C
P0.0
P3.7
ACC.2
05

; bit=1
; bit=0
; CY=1
;bit 0 from port 0 =1
;bit 7 from port 3 =1
;bit 2 from ACCUMULATOR =1
;set high D5 of RAM loc. 20h

Note:

CLR instruction is as same as SETB

i.e:
CLR
C
;CY=0
But following instruction is only for CLR:
CLR
A
;A=0

Bit Addressable
Page 359,360

SUBB

A,source ;A=A-source-CY

SETB C
SUBB A,R5

ADC
SETB C
ADC

;CY=1
;A=A-R5-1

A,source ;A=A+source+CY
;CY=1
A,R5

;A=A+R5+1

DEC
INC

byte
byte

;byte=byte-1
;byte=byte+1

INC
DEC
DEC

R7
A
40H

; [40]=[40]-1

CPL

;1s complement

Example:
L01:

MOV
CPL
MOV
ACALL
SJMP

NOP & RET & RETI

All are like 8086 instructions.

A,#55H ;A=01010101 B
A
P1,A
DELAY
L01

CALL

ANL - ORL - XRL

EXAMPLE:
MOV R5,#89H
ANL R5,#08H
RR RL RRC RLC A
EXAMPLE:
RR

Structure of Assembly
language and Running an
8051 program
EDITOR
PROGRAM

ORG
MOV
MOV
MOV
ADD
ADD
HERE: SJMP
END

0H
R5,#25H
R7,#34H
Myfile.lst
A,#0
A,R5
A,#12H
HERE

Myfile.asm
ASSEMBLER
PROGRAM
Other obj file
Myfile.obj
LINKER
PROGRAM

Myfile.abs
OH
PROGRAM
Myfile.hex

Memory mapping in 8051

ROM memory map in 8051 family

4k
0000H

8k

32k
0000H

0000H

0FFFH
DS5000-32
8751
AT89C51

1FFFH

from Atmel Corporation

8752
AT89C52

7FFFH

from Dallas Semiconductor

RAM memory space allocation in the 8051

7FH
Scratch pad RAM

30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0

8051 Flag bits and the PSW

register

PSW Register
CY

AC

F0

RS1

RS0

OV

Carry flag
Auxiliary carry flag
Available to the user for general purpose
Register Bank selector bit 1
Register Bank selector bit 0
Overflow flag
User define bit
Parity flag Set/Reset odd/even parity

RS1

RS0

Register Bank

--

PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0

CY
AC
-RS1
RS0
OV
-P

Address

00H-07H

08H-0FH

10H-17H

18H-1FH

Instructions that Affect Flag Bits:

Note: X can be 0 or 1

Example:
MOV
A,#88H
ADD
A,#93H
88
+93
---11B
CY=1
AC=0

10001000
+10010011
-------------00011011
P=0

Example:
MOV
A,#38H
ADD
A,#2FH
38
00111000
+2F +00101111
---- -------------67
01100111
CY=0
AC=1
P=1

Example:
MOV
A,#9CH
ADD
A,#64H
9C
+64
---100
CY=1
AC=1

10011100
+01100100
-------------00000000
P=0

Addressing Modes

Immediate
Register
Direct
Register Indirect

Immediate Addressing Mode

MOV
MOV
MOV
MOV
MOV

A,#65H
A,#A
R6,#65H
DPTR,#2343H
P1,#65H

Example :
Num EQU
30

MOV R0,Num
MOV DPTR,#data1

ORG 100H
data1:db
IRAN

Register Addressing Mode

MOV
ADD
MOV

Rn, A
A, Rn
DPL, R6

MOV
MOV

DPTR, A
Rm, Rn

;n=0,..,7

Direct Addressing Mode

Although the entire of 128 bytes of RAM can be accessed using direct
addressing mode, it is most often used to access RAM loc. 30 7FH.
MOV R0, 40H
MOV 56H, A
MOV A, 4
; MOV A, R4
MOV 6, 2
; copy R2 to R6
; MOV R6,R2 is invalid !

SFR register and their address

MOV
MOV
MOV

0E0H, #66H
; MOV A,#66H
0F0H, R2
; MOV B, R2
80H,A ; MOV P1,A

Bit Addressable
Page 359,360

Register Indirect Addressing Mode

In this mode, register is used as a pointer to the data.

MOV

A,@Ri

MOV

@R1,B

; move content of RAM loc.Where address is held by Ri into A

( i=0 or 1 )

In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB
insructions.
Example:
Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM
location starting at 59h.
Solution:
MOV R0,37h
MOV R1,59h
MOV R2,10
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,L1

; source pointer
; dest pointer
; counter

jump

On-Chip ROM Access

This mode is widely used in accessing data elements of

look-up table entries located in the program (code)
space ROM at the 8051
MOVC
A,@A+DPTR
A= content of address A +DPTR from ROM

Note:
Because the data elements are stored in the program
(code ) space ROM of the 8051, it uses the instruction
MOVC instead of MOV. The C means code.

Example:
Assuming that ROM space starting at 250h contains Hello., write a program to transfer the
bytes into RAM locations starting at 40h.
Solution:
ORG
0
MOV
DPTR,#MYDATA
MOV
R0,#40H
L1: CLR
A
MOVC
A,@A+DPTR
JZ
L2
MOV
@R0,A
INC
DPTR
INC
R0
SJMP
L1
L2: SJMP
L2
;------------------------------------ORG
250H
MYDATA:DB
Hello,0

END
Notice the NULL character ,0, as end of string and how we use the JZ instruction to
detect that.

Example:
Write a program to get the x value from P1 and send x 2 to P2, continuously .
Solution:
ORG
0
MOV DPTR, #TAB1
MOV A,#0FFH
MOV P1,A
L01:
MOV A,P1
MOVC A,@A+DPTR
MOV
P2,A
SJMP
L01
;---------------------------------------------------ORG
300H
TAB1: DB
0,1,4,9,16,25,36,49,64,81

END

MUL & DIV

MUL
AB ;B|A = A*B
MOV
A,#25H
MOV
B,#65H
MUL
AB ;25H*65H=0E99
;B=0EH, A=99H
MUL
AB ;A = A/B, B = A mod B
MOV
A,#25
MOV
B,#10
MUL
AB ;A=2, B=5

Stack in the 8051

7FH

The register used to access

the stack is called SP
(stack pointer) register. 30H

Scratch pad RAM

2FH
Bit-Addressable RAM

The stack pointer in the 20H

8051 is only 8 bits wide,1FH
which means that it can 18H
17H
10H
take value 00 to FFH.
When 8051 powered up, 0FH
08H
the SP register contains 07H
00H
value 07.

Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0

Example:
MOV
MOV
MOV
PUSH
PUSH
PUSH

R6,#25H
R1,#12H
R4,#0F3H
6
1
4

0BH

0BH

0BH

0BH

0AH

0AH

0AH

0AH

F3

09H

09H

09H

12

09H

12

08H

08H

08H

25

08H

25

Start SP=07H

25

SP=08H

SP=09H

SP=08H

LOOP and JUMP Instructions

DJNZ:

Write a program to clear ACC, then

add 3 to the accumulator ten time
Solution:
MOV
MOV
AGAIN: ADD
DJNZ
MOV

A,#0;
R2,#10
A,#03
R2,AGAING ;repeat until R2=0 (10 times)
R5,A

Other conditional jumps :

JZ

Jump if A=0

JNZ

Jump if A/=0

DJNZ

Decrement and jump if A/=0

CJNE A,byte

Jump if A/=byte

CJNE reg,#data

Jump if byte/=#data

JC

Jump if CY=1

JNC

Jump if CY=0

JB

Jump if bit=1

JNB

Jump if bit=0

JBC

Jump if bit=1 and clear bit

CJNE , JNC
Exercise:
Write a program that compare R0,R1.
If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2.

CALL Instructions
Another control transfer instruction is the CALL
instruction, which is used to call a subroutine.

LCALL(long call)
In this 3-byte instruction, the first byte is the opcode
an the second and third bytes are used for the
address of target subroutine. Therefore, LCALL can
be used to call subroutines located anywhere within
the 64K byte address space of the 8051.

ACALL (absolute call)

ACALL is 2-byte instruction in contrast to LCALL,
which is 13 bytes. Since ACALL is a 2-byte instruction,
the target address of the subroutine must be within 2K
bytes address because only 11 bits of the 2 bytes are used
for the address. There is no difference between ACALL
and LCALL in terms of saving the program counter on
the stack or the function of the RET instruction. The only
difference is that the target address for LCALL can be
anywhere within the 64K byte address space of the 8051
while the target address of ACALL must be within a 2Kbyte range.