ECE 448

Lecture 15
ASICs vs. FPGAs

ECE 448 FPGA and ASIC Design with VHDL

George Mason University

FPGAs vs. ASICs

ASICs
High performance

FPGAs
Off-the-shelf
Low development costs

Low power
Short time to the market
Low cost (but only
in high volumes)

ECE 448 FPGA and ASIC Design with VHDL

Reconfigurability

ASIC Design Example Factoring circuit/GMU

Global Memory

Local
Memory

ECE 448 FPGA and ASIC Design with VHDL

ASIC 130 nm vs. Virtex II 6000

Factoring/GMU

19.68 mm

19.80 mm

51x

Area of Xilinx Virtex II 6000

FPGA
(estimation by R.J. Lim Fong,
MS Thesis, VPI, 2004)

2.7 mm
2.82 mm

Area of an ASIC with equivalent functionality

ECE 448 FPGA and ASIC Design with VHDL

ASICs vs. FPGAs

Source:
I. Kuon, J. Rose,
University of Toronto
Measuring the Gap Between
FPGAs and ASICs
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems,
vol. 62, no. 2, Feb 2007.

ECE 448 FPGA and ASIC Design with VHDL

ASICs vs. FPGAs

23 representative circuits implemented using
FPGAs and ASICs
- computer arithmetic (booth, cordic18, cordic8, etc.)
- digital signal processing (rs_encoder, fir3, fir24,
etc.)
- communications (ethernet, mac1, atm, etc.)
- cryptography (des_area, des_perf, aes, aes192,
etc.)
- scientific computations (molecular, raytracer, etc.)
ECE 448 FPGA and ASIC Design with VHDL

ECE 448 FPGA and ASIC Design with VHDL

ECE 448 FPGA and ASIC Design with VHDL

ECE 448 FPGA and ASIC Design with VHDL

ECE 448 FPGA and ASIC Design with VHDL

10

ASIC Design Flow

Algorithm
Specification
RTL Design
Verilog, VHDL

Reference
Implementation
C, C++

Synopsys Design Compiler

stdcell lib

Logic Synthesis

Layout

VCS

Hercules
Calibre

die area
pin count

LVS

Mentor Calibre
Synopsys StarRCXT

Parasitic Extraction

latency
throughput
(post-synthesis)

Simulation

Synopsys IC Compiler
Cadence Encounter

process lib

Design
Quality

test vectors

VCD

Simulation
PrimeTime

latency
throughp
ut
(post
P&R)
power diss
11

Simplified ASIC Design Flow

Front-End
Design
Back-End
Design

Synthesis
Timing Analysis
Floorplanning
Placement
Clock Tree Synthesis
Routing
Design for Manufacturing

ECE 448 FPGA and ASIC Design with VHDL

12
31

Major ASIC Toolsets

Cadence
Magma

ECE 448 FPGA and ASIC Design with VHDL

13

Simplified ASIC Design Flow

Front-End
Design
Back-End
Design

Synthesis
Timing Analysis

Synopsys
Tools

Design Compiler
Primetime

Floorplanning
Placement
Clock Tree Synthesis

Astro

Routing
Design for Manufacturing
ECE 448 FPGA and ASIC Design with VHDL

14
31

A Complete Placed and Routed Chip

IP

ECE 448 FPGA and ASIC Design with VHDL

15
28

Digital system design technologies

coverage in the CpE & EE programs at GMU
Microprocessors
ECE 445

ASICs

FPGAs

Computer
Organization

ECE 431
Digital Circuit Design

ECE 447

Single Chip
Microcomputers

ECE 448
FPGA and ASIC Design with VHDL

ECE 511
ECE 611

Microprocessors
Advanced
Microprocessors

ECE 545
ECE 645

Digital System Design with VHDL

Computer Arithmetic

ECE 586

Digital
Integrated
Circuits

ECE 681

VLSI Design
for ASICs

DIGITAL SYSTEMS DESIGN

1. ECE 545 Digital System Design with VHDL
K. Gaj, project, FPGA design with VHDL, Aldec/Xilinx/Altera
2. ECE 645 Computer Arithmetic
K. Gaj, project, FPGA design with VHDL or Verilog,
Aldec/Xilinx/Altera/Synopsys
3. ECE 586 Digital Integrated Circuits
D. Ioannou
4. ECE 681 VLSI Design for ASICs
N. Klimavicz, project/lab, front-end and back-end ASIC design with
Synopsys tools
5. ECE 682 VLSI Test Concepts
T. Storey, homework