Anda di halaman 1dari 15

PowerPC Architecture

POWER stands for Performance Optimization with


Enhanced RISC
History
IBM (1990) introduced POWER in 1990 with RS/6000
IBM, Apple, and Motorola formed an alliance to develop
PowerPC in 1991
The first products were delivered near the end of 1993
Recent implementations include PowerPC 601, 603, 604

PowerPC Architecture

Memory
halfword, word, doubleword, quadword
may instructions may execute more efficiently if operands
are aligned at a starting address that is a multiple of their
length
virtual space 264 bytes
fixed-length segments, 256 MB
fixed-length pages, 4KB
MMU: virtual address -> physical address

PowerPC Architecture

Registers
32 general-purpose registers, GPR0~GPR31
FPU
condition code register reflects the result of certain
operations, and can be used as a mechanism for testing and
branching
Link Register (LR) and Count Register (CR) are used by
some branch instructions
Machine Status Register (MSR)

PowerPC Architecture

Data Formats
integers are 8-, 16-, 32-, 64-bit binary numbers
2s complement is used for negative values
support both big-endian (default) and little-endian byte
orderings
three different floating-point data formats
single-precision, 32 bits long (23 + 8 + 1)
double-precision, 64 bits long (52 + 11 + 1)

characters are stored using 8-bit ASCII codes

PowerPC Architecture

Seven Instruction Formats

32 bits long
the first 6 bits identify specify the opcode
some instruction have an additional extended opcode
the complexity is greater than SPARC
fixed-length makes decoding faster and simple than VAX
and x86

PowerPC Architecture

Addressing Modes
immediate mode, register direct mode
memory addressing
Mode
Register indirect

Target address calculation

TA=(register)
Register indirect with indexed
TA=(register-1)+(register-2)
Register indirect with
TA=(register)+displacement {16 bits, signed}
immediate indexed

branch instruction
Mode
Absolute

Target address calculation

TA= actual address


Relative
TA= current instruction address + displacement {25 bits, signed}
Link Register
TA= (LR)
Count Register
TA= (CR)

PowerPC Architecture

Instruction Set
200 machine instructions
more complex than most RISC machines
e.g. floating-point multiply and add instructions that take three
input operands
e.g. load and store instructions may automatically update the
index register to contain the just-computed target address

pipelined execution
more sophisticated than SPARC

branch prediction

PowerPC Architecture

Input and Output


two different modes
direct-store segment: map virtual address space to an external
address space
normal virtual memory access

Cray T3E Architecture

Cray Research, Inc. (1995)


Massively parallel processing system (MPP)
Scientific computing
T3E
16~2048 processing elements (PE)
three-dimensional network
each PE consists of a DEC Alpha EV5 RISC microprocessor, local
memory, and performance-accelerating control logic

Cray T3E Architecture

Local Memory

64MB ~ 2GB
physically distributed, logically shared memory
byte, word, longword, quadword
64-bit virtual addresses

10

Cray T3E Architecture

Registers
32 general-purpose registers, GPR0~GPR31
32 floating-point registers, F0~F31
F31 always contain the value zero

program counter PC
other status and control registers

11

Cray T3E Architecture

Data Formats
two different types of floating-point data formats
one for compatibility with VAX
the other for IEEE standard formats

characters are stored using 8-bit ASCII codes


since there are no byte load or store operations, characters that
are to be manipulated separately are usually stored one per
longword

12

Cray T3E Architecture

Five Basic Instruction Formats


32 bits long
the first 6 bits identify specify the opcode
some instruction have an additional function field

13

Cray T3E Architecture

Addressing Modes
immediate mode, register direct mode
memory addressing
Mode

Target address calculation

PC-relative
Register indirect with
displacement

TA=(PC)+displacement {23 bits, signed}


TA=(register)+displacement {16 bits, signed}

register indirect with displacement mode is used for load and


store operations and for subrountine jumps
PC-relative mode is used for conditional and unconditional
branches

14

Cray T3E Architecture

Instruction Set
130 machine instructions
no byte or word load and store instructions

15