Introduction To Vhdl-2ec313-Dsd-Ad

VHDL
-Combinational Circuits
Lecture 4
Amit Degada
Asst Prof, EC
IT-NU
Amit.degada@nirmauni.ac.in
Presentation Outline
Why HDLs
Feature of HDL
HDL Implementation Design
Cycle
Advantage of HDL
A Brief History of VHDL
Writing Code
Other HDLs
Verilog
Paracore http://www.dilloneng.com/paracore.shtml
Ruby HDL
http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
My HD
JHDL http://www.jhdl.org/
Lava http://www.xilinx.com/labs/lava/
HDL maker http://www.polybus.com/hdlmaker/users_guide/
System C
AHDL http://www.polybus.com/hdlmaker/users_guide/
Sequential Language
Statements execute one at a time in a
sequential manner
Sequence of the statements is important as in

case of conventional language
Statement-1
Statement-2
Statement-n
Why HDLs?
In software everything is sequential
Sequence of statements is significant, since they
are executed in that order
In hardware events are concurrent, so a software
language cannot be used for describing and
simulating hardware.
Example
C = (not (X) and Y) or (not (X))
Case 1
A = not X
B = A and Y
C = A or B
Result:
C=1
Case 2
B = A and Y
C = A or B
A = not X
Result:
C=0
Case 3
C = A or B
A = not X
B = A and Y
Result:
C=0
Technology Independence
The design of VHDL components can be technologyindependent or more-or-less technology independent for a
technical family
The components can be stored in a library for reuse in several
different designs
VHDL models of commercial IC standard components can now
be bought, which is a great advantage when it comes to verifying
entire circuit boards
Design Level
HDL Implementation Design Cycle

This is Very Simple flow:
consider the one which is
given in lab manual as
perfect on
Advantage of Using Hardware Description

Language
Designs can be described at various levels of abstractions
Top-Down Approach and hierarchical designs for large projects
Functional Simulation Early in the Design Flow
Automatic Conversion of HDL Code to Gates
With user level control. Consistent quality. Fast.
Early Testing of Various Design Implementations
Due to fast synthesis, there is a scope for trying different implementations.
Design Reuse
Technology independence, standardization, portability, ease of maintenance.
All this results in low risk, high convergence, fast time to market,
more money.
What is VHDL?
VHDL Stands for
VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language.
About VHDL
VHDL is not case sensitive
VHDL is a free form language. You can write the
whole program on a single line.
-- This is a VHDL comment
entity my_exor is -- one more comment
Port(
...);
end my_exor;
Entity Syntax
entity <name> is
[generic(
<gen_name> : <type*>[:=<init>];
.
.
. )]
port (
<port_name> : <dir**> <type>;
.
.
. );
end <name>;
* <type> is any VHDL type
** <dir> is a direction of the port:
IN, OUT, or INOUT
my EXOR gate
-- This is my first VHDL program
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;
entity
entitydeclaration
declaration--describes
describesthe
the
boundaries
boundariesof
ofthe
theobject.
object.
It
Itdefines
definesthe
thenames
namesof
ofthe
theports,
ports,
Their
Theirmode
modeand
andtheir
theirtype.
type.
my EXOR gate
library IEEE;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;
entity
entity--defines
definesthe
the
interface.
interface.
Mode
Modeof
ofthe
theport
port::
Direction
Directionof
offlow.
flow.
It
Itcan
canbe
be
in,
in,out,
out,inout,
inout,buffer
buffer
my EXOR gate
library IEEE;
entity
entity my_exor is
entity--defines
definesthe
the
interface.
port (ip1
: in std_logic;
interface.
ip2
: in std_logic;
op1
: out std_logic
);
std_logic
std_logicis
isthe
thetype
typeof
ofthe
the
Mode
Modeof
ofthe
theport
port: :
end my_exor;
port.
ItItcan
port.
canbe
be
Standard
in,
Standardlogic
logicis
isdefined
defined
in,out,
out,inout,
inout,buffer
buffer
by
bythe
thestandard
standard
IEEE
IEEE1164.
1164.
It
Itis
isdefined
definedin
inthe
theIEEE
IEEE
library.
library.
Any
Anynode
nodeof
oftype
typestd_logic
std_logic
can
cantake
take99different
differentvalues.
values.
0
0,,1
1,,H
H,,L
L,,Z
Z,,
U
U,,X
X,,W
W,,-
-
my EXOR gate
library IEEE;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;
Library
Library::Collection
Collectionof
ofdesign
design
elements,
elements,type
typedeclarations,
declarations,
sub
subprograms,
programs,etc.
etc.
my EXOR gate
--Program 1.1
library IEEE;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
Mode
Modeof
ofthe
theport
port: :
);
ItItcan
canbe
be
end my_exor;
in,
out
in, outor
orinout
inout
Library
Library: :Collection
Collectionof
ofdesign
design
elements,
type
declarations,sub
elements, type declarations,sub
programs,
programs,etc.
etc.
entity
entity--defines
definesthe
the
interface.
interface.
std_logic
std_logicisisthe
thetype
typeof
ofthe
theport
port
ItItis
isdefined
definedin
inthe
theIEEE
IEEElibrary.
library.
Any
Anynode
nodeof
oftype
typestd_logic
std_logiccan
cantake
take
99different
values.
different values.
0,1,H,L
0,1,H,L, ,Z
Z, ,U
U, ,X
X, ,W
W, ,-
-
architecture my_exor_beh of my_exor is

begin
The
op1 <= (ip1 and (not ip2)) or
Thearchitecture
architecturedescribes
describesthe
the
behaviour
(function),
(ip2 and (not ip1));
behaviour (function),
interconnections
end my_exor_beh;
interconnectionsand
andthe
the
relationship
relationshipbetween
betweendifferent
different
inputs
inputsand
andoutputs
outputsof
ofthe
theentity.
entity.
my EXOR gate
library IEEE;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
Mode
end my_exor;
Modeof
ofthe
theport
port: :
ItItcan
canbe
be
in,
out
or
in, out orinout
inout
architecture my_exor_beh of my_exor is

begin
op1 <= (ip1 and (not ip2)) or
(ip2 and (not ip1));
end my_exor_beh;
configuration my_exor_C of my_exor is
for my_exor_beh
end for;
end my_exor_C;
Library
Library: :Collection
Collectionof
ofdesign
design
elements,
type
declarations,
elements, type declarations,
sub
subprograms,
programs,etc.
etc.
entity
entity- -defines
definesthe
the
interface.
interface.
std_logic
std_logicisisthe
thetype
typeof
ofthe
theport
port
ItItisisdefined
in
the
IEEE
library.
defined in the IEEE library.
Any
node
Any nodeof
oftype
typestd_logic
std_logiccan
cantake
take
99different
value.
different value.
0
0, ,1
1, ,H
H, ,L
L, ,Z
Z, ,U
U, ,X
X, ,W
W, ,-
-
The
Thearchitecture
architecturedescribes
describesthe
the
behaviour(function),
interconnections
behaviour(function), interconnections
and
andthe
therelationship
relationshipbetween
betweendifferent
different
inputsand
outputs.
inputsand outputs.
The
Theconfiguration
configurationisisoptional.
optional.
ItItdefines
the
entity
architecture
defines the entity architecture
bindings.
bindings.
More
Moreabout
aboutconfigurations
configurationslater.
later.
Internal connections are made using signals.

Signals are defined inside the architecture.
architecture
architecture my_exor_beh
my_exor_beh of
of my_exor
my_exor is
is
signal
signal temp1
temp1 :: std_logic;
std_logic;
signal
signal temp2
temp2 :: std_logic;
std_logic;
begin
begin
......
......
end
end my_exor_beh;
my_exor_beh;
my EXOR with internal

signals(dataflow)
--Program
1.2
--Program 1.2
library
library IEEE;
IEEE;
use
IEEE.std_logic_1164.all;
entity
entity my_exor
my_exor is
is
port
(ip1
:
in
port (ip1
: in std_logic;
std_logic;
ip2
ip2 :: in
in std_logic;
std_logic;
op1
op1 :: out
out std_logic
std_logic
);
);
end
my_exor;
end my_exor;
architecture
architecture exor_w_sig
exor_w_sig of
of my_exor
my_exor is
is
signal
temp1,
temp2
:
std_logic;
signal temp1, temp2 : std_logic;
begin
begin
temp1
temp1 <=
<= ip1
ip1 and
and (not
(not ip2);
ip2);
temp2
<=
ip2
and
(not
ip1);
temp2 <= ip2 and (not ip1);
op1
op1 <=
<= temp1
temp1 or
or temp2;
temp2;
end
exor_w_sig;
end exor_w_sig;
configuration
configuration my_exor_C
my_exor_C of
of my_exor
my_exor is
is
for
for exor_w_sig
exor_w_sig
end
end for;
for;
end
my_exor_C;
end my_exor_C;
Syntax of an Architecture
architecture <name> of <entity> is
<declarations>
begin
<statements>
end <name>;
Other VHDL resources

VHDL mini-reference by Prof. Nelson
http://www.eng.auburn.edu/department/ee/m
gc/vhdl.html
VHDL Tutorial: Learn by Example

by Weijun Zhang
http://esd.cs.ucr.edu/labs/tutorial/
23
Presentation Outline
Signal in VHDL
Types of Architecture
Some intuitive way to find diff bet
architectures
VHDL Design Example: Combinational
Circuits
24
Lect Intro
Oh yeah, For all you C people --forget
everything you know.
Well, not EVERYTHING ... :)

But VHDL is NOT C ...
There are some similarities, as with any programming
language, but syntax and logic are quite different; so get
over it!!! :)
18/10/15
Prof Amit Degada
25
Register Transfer Logic (RTL) Design

Description
Todays Topic
Combinational
Logic
Combinational
Logic
Registers
Prof Amit Degada
Signals
SIGNAL a : STD_LOGIC;
a
1
wire
SIGNAL b : STD_LOGIC_VECTOR(7
DOWNTO 0);
bus
Prof Amit Degada
my EXOR with internal

signalsIEEE;
library
library IEEE;
use
IEEE.std_logic_1164.all;
entity
entity my_exor
my_exor is
is
port
(ip1
:
in
port (ip1
: in std_logic;
std_logic;
ip2
:
in
std_logic;
ip2
: in std_logic;
op1
op1 :: out
out std_logic
std_logic
);
);
end
my_exor;
end my_exor;
architecture
architecture exor_w_sig
exor_w_sig of
of my_exor
my_exor is
is
signal
signal temp1,
temp1, temp2
temp2 :: std_logic;
std_logic;
begin
begin
temp1
temp1 <=
<= ip1
ip1 and
and (not
(not ip2);
ip2);
temp2
<=
ip2
and
(not
ip1);
temp2 <= ip2 and (not ip1);
op1
op1 <=
<= temp1
temp1 or
or temp2;
temp2;
end
end exor_w_sig;
exor_w_sig;
configuration
configuration my_exor_C
my_exor_C of
of my_exor
my_exor is
is
for
exor_w_sig
for exor_w_sig
end
end for;
for;
end
end my_exor_C;
my_exor_C;
Functional Delay
Syntax: Concurrent statement AFTER
delay;
REMEMBER: Its functional delay, not
inherent delay
ARCHITECTURE dataflow OF xor_gate IS
BEGIN
f <= (a AND NOT b) OR (NOT a AND b)
AFTER 20 ns;
END dataflow;
Entity
Equivalent to pin configuration of an IC
Syntax
entity entity_name is
port (port_list);
end entity_name
Example:
entity not_gate is
port ( a1,a2,a3: in std_logic;
a4,a5,a6: in std_logic;
b1,b2,b3:out std_logic;
b4,b5,b6:out std_logic
);
end not_gate;
1
4
1
3
1
2
1
1
1
0
Entity
VHDL design description must include,
- only one entity
- at-least one corresponding architecture.
Entity declaration
- Defines the input and output ports of the design
- Each port in the port list must be given
- a name
- data flow direction
- a type
Can be used as a component in other entities after being
compiled into library
Entity
Proper documentation of the ports in an entity is very
important
A specified port should have a self explanatory name that

provides information about its function.
Port should be well documented with the comments at the
end of the line providing additional information about the signal
Consider the example of ALU
in1
cin
in2
opsel mode
cou
t
ALU
result
Entity
entity ALU is
port (
in1 : in std_logic_vector(3 downto 0);
operand
in2 : in std_logic_vector(3 downto 0);
operand
opsel: in std_logic_vector(3 downto 0);
sel.
cin : in std_logic;
-- carry
mode: in std_logic;
--mode
arithmetic/logic
in1 in2 opsel mode
result: out std_logic_vector (3 downto 0);
result
cou
cout: out std_logic);
cin
ALU
t
carry output
end ALU
result
-- first
-- second
-- operation
input
--operation
--
Modes
Signal in the port has a mode which indicates the driver
direction
Mode also indicate whether or not the port can be read
from within the entity
Four types of modes are used in VHDL
- mode IN
- mode OUT
- mode INOUT
- mode BUFFER
The assignment of hardware I/O buffers to the ports (push-pull, tristate, differential output, etc.) depends on the implementation and the
target technology .
Use of buffer ports is not recommended.
Mode IN
Value can be read but not assigned
Example:
entity driver is
port (
A: in std_logic;
B: out std_logic;
data: inout std_logic;
count: buffer std_logic
);
end driver;
Entity
Port
signal
A
Driver reside
outside the entity
Mode OUT
Value can be assigned but not read
Entity
Example:
entity driver is
port (
A: in std_logic;
B: out std_logic;
);
end driver;
Port
signal
Driver reside
inside the entity
Mode INOUT
Value can be read and assigned
Example:
entity driver is
port (
A: in std_logic;
B: out std_logic;
);
end driver;
Port signal
Entity
data
Driver may reside both

inside and outside the
entity
Mode BUFFER
Output port with internal read capability

Entity
Example:
entity driver is
port (
A: in std_logic;
B: out std_logic;
);
end driver;
Port
signal
coun
t
Driver reside
inside the entity
Architecture
An architecture specifies the behavior, function, interconnections and the

relationship between the inputs and the outputs of an entity.
An entity can have more than one architecture .

There can be no architecture without an entity .
Each architecture is bound to an entity using the configuration

statement .
Architectures can have various abstraction levels and
implementations to facilitate faster design, better understanding,
better performance and lesser complexity. Some of these aspects
may be mutually exclusive where some amount of compromise
needs to be arrived at.
Prof Amit Degada
VHDL Architecture Design Styles

VHDL Design
Styles
Test benches
dataflow
Concurrent
statements
structural
Components and
interconnects
behavioral
(sequential)
Sequential statements
Registers
State machines
Instruction decoders
Subset most suitable for synthesis

Prof Amit Degada
VHDL Arch 4 ways of doing it

Dataflow
Behavioral
Structural
Mics ( Combination of two or more)
Sounds boring initially,
but The Things get excited with Examples :)
Prof Amit Degada
Architecture- An intuitive way

VHDL architectures can be classified as
Behavioral
Defines a sequentially described functioning of
the design.
Set of sequential statements.
Dataflow
More like a Boolean equation .
Set of concurrent Assignments.
Structural
Defines interconnections between previously
defined components.
Prof Amit Degada
Architecture
architecture [architecture_name] of [entity_name] is
[declarations]
begin
[statements]
end [ architecture_name ];
Prof Amit Degada
1 bit Half Adder

For a one-bit add, the sum is just the XOR of the inputs, and the
carry out is just the AND
Carry = A.B
Entity HA_AD is
port ( A, B : in std_logic;
Sum, Carry : out std_logic);
End HA_AD;
Prof Amit Degada
1 bit Half Adder- Behavioral

architecture behavioral of HA_AD
is
begin
process(A,B)
begin
if(A/=B) then
Sum <=
'1';
else
Sum <=
'0';
end if;
end process;
process(A,B)
begin
if((A='1') and
(B='1')) then
Carry <=
'1';
else
Note:
It contains sequential
statements
Use of ifelse if, case,
45
Data-Flow VHDL
Concurrent Statements
Concurrent signal assignment

()
Conditional concurrent signal assignment

(when-else)
Selected concurrent signal assignment

(with-select-when)
Generate scheme for equations

(for-generate)
Prof Amit Degada
46
1 bit Half Adder- Data Flow

architecture data_flow of
HA_AD is
Note:
begin
like Boolean Equation

Sum <= A xor B; More
It contains concurrent
Carry <= A and B; statements
end data_flow;
<= is concurrent Assignments
Prof Amit Degada
1 bit Half Adder- Structural

x
Z
Y
Define overall
system
P
R
Q
Composed of
2
Components
XOR, AND
Gate
1 bit Half Adder- Strutural

Component should be defined in .vhd file in your directory
before you call it
architecture [arch_Identifier] of [entity_identifier] is
component [component_identifier]
port(X, Y : in std_logic; Z : out std_logic);
defined in entity
end component;
--Same as you
component [component_identifier]
--Another Component
port(P,Q : in std_logic; R: out std_logic);
end component;
Signals, variables
begin
label 1: [component identifier] port map ( )
label 1: [component identifier] port map ( )
end [arch_Identifier]
1 bit Half Adder- Structural

architecture structural of HA_ad is
component xor_gate
port(X, Y : in std_logic; Z : out std_logic);
end component;
component and_gate
port(P,Q : in std_logic; R: out std_logic);
end component;
begin
G1: xor_gate port map (A,B,Sum);
G3: and_gate port map (A,B,Carry);
end structural;
Prof Amit Degada
1 bit Full Adder

A full adder is a logical circuit that performs an addition
operation on three one-bit binary numbers(A, B and Cin)
Entity FA_AD is
port ( A, B, Cin : in
std_logic;
S, Co : out
std_logic);
End FA_AD;
1 bit Full Adder- Behavioral

Code.
Process Statement
A process statement contains sequential
statements that describe the functionality of a
portion of an entity in sequential terms.
Syntax:
[process-label:] process [(sensitivity-list)] [is]
[process-itemdeclarations]
begin
Sequential statements; these are
variable-assignmentstatement,
waitstatements,
if- statement,
case-statement and so on..
end process [process label];
Process Statement
A set of signal to which process
signal is sensitive is defined
by the sensitivity list.
Sequential statements within the
process are executed in a
sequential order, that is, in the
order in which they appear.
Items declared in the item
declarations part is available for
use only within the process.
Process statement
The process concept comes from software and can be compared to a
sequential program.
If there are several processes in an architecture, they are executed concurrently.
A process can be in Waiting or Executing state.
Executing
Waiting
If the state is Waiting, a condition

start must be satisfied, e.g. wait
until clk=1;.
This means that the process will start when clk has a rising
edge.
Then the process will be Executing.
Once it has executed the code, it will wait for the next rising
edge.
The condition after the until means not only the necessity of the
value 1, but also the necessity of changing the value to 1.
WAIT statement Syntax
The wait statement causes the suspension of a process

statement.
wait [sensitivity_clause] [condition_clause]
[timeout_clause];
Sensitivity_clause ::= on signal_name
wait
on
CLOCK;
Condition_clause ::= until boolean_expression

wait
until
Clock = 1;
Timeout_clause ::= for time_expression

wait
for
150 ns;
Example to test the wait until

command - circuit description
entity cir is
port (a,clk: in bit; y: out bit);
end;
architecture bhv of cir is
begin
process (clk)
begin
y <= a;
wait until 10 ns;
end process;
end;
Concurrent Process
Equivalents
All concurrent statements correspond to a
process equivalent.
U0: q <= a xor b after 5 ns;
is short hand notation for
U0: process
begin
q <= a xor b after 5 ns;
wait on a, b;
end process;
Sensitivity-lists vs Wait-on statement
Variable assignment
Variables can bestatement
declared and used inside a
process statement
Variable identifier : type [:=initial value] ;
e.g. variable sum : bit ;
A variable is assigned a value using the variable
assignment statement that is typically has the form;
variable-object := expression;
The expression is evaluated when the statement is
executed, and the computed value is assigned to the
variable object instantaneously, that is, at the
current simulation time
Differences between signals and variables

Sum1 and sum2 are
variables
Sum1 and sum2 are signals

p0: process
begin
wait for 10 ns;
sum1<=sum1+1;
sum2<=sum1+1;
end process;
Time
0
10
10 +
20
20 +
30
30 +
p1: process
variable sum1, sum2:
integer;
begin
wait for 10 ns;
sum1:=sum1+1;
sum2:=sum1+1;
end process;
Sum1 Sum2 Sum1 Sum2
0
0
1
1
2
2
3
0
0
1
1
2
2
3
0
1
1
2
2
3
3
0
2
2
3
3
4
4
Information transfer
Variables cannot transfer information outside the sequential part of VHDL in
which it is declared, in the previous example process p1.
If access is needed to the value of sum1 or sum2, they must be declared as
signals/out or the value of the variable assigned to a signal.
Entity ex is
port(sum1_sig, sum2_sig: out
integer);
end;
Architecture bhv of ex is
begin
p1: process
variable sum1, sum2:
integer;
begin
wait for 10 ns;
sum1:=sum1+1;
sum2:=sum1+1;
sum1_sig<=sum1;
sum2_sig<=sum2;
end process;
end;
Case Statement
[ case _label : ] case expression is
{ case_statement_alternative }
end case [ case _label ];

Example:
case a is
when '0' => q <= "0000" after 2 ns ;
when '1' => q <= "1111" after 2 ns ;
end case;
The value of bit a is checked. If it is 0 then q is
assigned the value 0000 after 2 ns, otherwise it is
assigned the value 1111 , also after 2 ns
Conditional concurrent signal

assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
...
valueN-1 when conditionN-1
else
Default_value;
Prof Amit Degada
Most often implied structure

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
...
valueN-1 when conditionN-1
else
valueN;
Value N
Value N-1
0
1
0
1
0
1
Value 2
Value 1
Condition N-1
Condition 2
Condition 1
Prof Amit Degada
Target Signal
Most Often Implied Structure

With Select When
with choice_expression select
target_signal <= expression1 when
choices_1,
expression2 when
choices_2,
...
when
choices_1
expression1 expressionN
expression2
choices_2
choices_N;
target_signal
expressionN
choices_N
choice expression
Prof Amit Degada
Selected concurrent signal

assignment
With Select-When
with choice_expression select
target_signal <= expression1 when
choices_1,
expression2 when
choices_2,
...
expressionN when
choices_N;
Multiplexer
IN0
IN1
IN2
IN3
4: 1
Multiplex
er
S0 S1
Output
Multiplexer
The multiplexer is described in VHDL with following statements
IF
CASE
WHEN Else
WITH select When.
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
numerical computation.
Entity mux4_1 is
port ( s0 : in std_logic;
s1 : in std_logic;
in0 : in std_logic;
in1 : in std_logic;
in2 : in std_logic;
in3 : in std_logic;
output : out std_logic );
End mux4_1;
-- package to be include
-- provides unsigned
IF
Architecture if_example of mux4_1 is
Statement
Begin
Mux: process(s0, s1, in0, in1, in2, in3)

Begin
if (s0='0' and s1='0') then

output <= in0;
elsif (s0='1' and s1='0') then
output <= in1;
output <= in2;
output <= in3;
else
output <= Z';
-- s0 or s1 are not 0 or 1
end if;
End process mux;
End if_example;
CASE
Statement
ARCHITECTURE case_example
OF mux4_1 IS
BEGIN
mux: PROCESS (s0, s1, in0, in1, in2, in3)
VARIABLE sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
sel := s1 & s0;
-- concatenate s1 and s0
CASE sel IS
WHEN "00" => output <= in0;
WHEN OTHERS => output <= 'X';
END CASE;
END PROCESS mux;

END case_example;
When
ARCHITECTUREStatement
when_example OF mux4_1 IS
BEGIN
output <= in0 WHEN (s1 & s0)="00" ELSE

in1 WHEN (s1 & s0)="01" ELSE
'X';
END when_example;
WITH-SELECT-WHEN
Statement
ARCHITECTURE with_example OF mux4_1 IS
SIGNAL sel : STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
sel <= s1 & s0;
-- concatenate s1
and s0
WITH sel SELECT
output <= in0 WHEN "00",
in1 WHEN "01",
in2 WHEN "10",
in3 WHEN "11",
'X' WHEN OTHERS;
END with_example;
Mics style of Architecture modelling

Its Possible to mix more two or more than two style of
Architecture
architecture FA_MIXED of FULL_ADDER is
component XOR2
port(P1,P2: in BIT; PZ: out BIT);
end component;
signal S1: BIT;
begin
X1:XOR2 port map (A,B,S1);
process(A,B,CIN)
variable T1,T2,T3: BIT;
begin
T1 := A and B;
T2 := B and CIN;
T3 := A and CIN;
COUT <= T1 or T2 or T3;
end process;
SUM <= S1 xor CIN;
end FA_MIXED;
Prof Amit Degada
75
Priority of logic and relational

operators
compare
Incorrect
when a = b and c else
equivalent to
when (a = b) and c else
Correct
when a = (b and c) else
Prof Amit Degada
a = bc
Logic Operators
and
xnor
or
nand
nor
xor
not is not part of Logical operator but

its Miscellaneous operator Having
Highest Priority
Highest
and
or
not
nand
nor
not
only in VHDL-93
or later
xor
xnor
Lowest
77
Prof Amit Degada
Operators
Relational operators
/=
<
<=
>
>=
Logic and relational operators

precedence
Highest
Lowest
not
=
/=
<
<= >
>=
and or nand nor xor xnor
Prof Amit Degada
78
Operators and Operators Prescedence
xnor and shift

VHDL93
only !!
Precedence can be overridden by use of parentheses.
Precedence of operators is maintained even after overloading.
No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
Prof Amit Degada
Merging wires and buses

a
4
10
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a: STD_LOGIC_VECTOR(3 DOWNTO 0);

b: STD_LOGIC_VECTOR(4 DOWNTO 0);
c: STD_LOGIC;
d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;
Splitting buses
a
4
10
5
b
c
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a: STD_LOGIC_VECTOR(3 DOWNTO 0);

b: STD_LOGIC_VECTOR(4 DOWNTO 0);
c: STD_LOGIC;
d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);

b <= d(5 downto 1);
c <= d(0);
Sequential Hardware
You have to distinguish between
combinational, latches and synchronized
Flip-Flops
Lack of understanding is a common source
of errors.
We will first cover latches,
Next we will cover flip-flops
D latch
Graphical symbol
D
Truth table
Q(t+1)
Clock D
0
1
1
Clock
0
1
Q(t)
0
1
Timing diagram
Clock
t1
t2
t3
t4
D
Q
Time
D latch
library ieee;
use ieee.std_logic_1164.all;
entity dlatch_my is
port(D, Clock : in std_logic;
Q : out std_logic);
end dlatch_my;
architecture dlatch of dlatch_my is
begin
process(D,Clock)
begin
if (Clock = '1') then
Q <= D;
end if;
end process;
end architecture;
D
Clock
D flip-flop
Graphical symbol
D
Truth table
Clk D
Clock
Timing diagram
Clock
t1
t2
t3
0
1
0
1
Q(t+1)
0
1
Q(t)
Q(t)
t4
D
Q
Time
D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock
: IN STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE behavioral OF flipflop IS
BEGIN
PROCESS ( Clock, D )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
D
Clock
D flip-flop
LIBRARY ieee ;
ENTITY flipflop IS
PORT (
D, Clock : IN STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE behavioral2 OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral2;
Clock
D flip-flop
LIBRARY ieee ;
ENTITY flipflop IS
PORT ( D, Clock
: IN STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE behavioral3 OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(Clock) ;
Q <= D ;
END PROCESS ;
END behavioral3 ;
Clock
D flip-flop with asynchronous reset

LIBRARY ieee ;
ENTITY flipflop_ar IS
PORT ( D, Resetn, Clock : IN
Q
: OUT
END flipflop_ar ;
STD_LOGIC ;
STD_LOGIC) ;
ARCHITECTURE behavioral OF flipflop_ar IS

BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
Q
D
Clock
Resetn
D flip-flop with synchronous reset

LIBRARY ieee ;
ENTITY flipflop_sr IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop_sr ;
ARCHITECTURE behavioral OF flipflop_sr IS

BEGIN
PROCESS(Clock)
BEGIN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END behavioral ;
D
Clock
Resetn
Asynchronous vs. Synchronous

In the IF loop, asynchronous items are
Before the rising_edge(Clock)
statement
In the IF loop, synchronous items are

After the rising_edge(Clock) statement
8- bit register with asynchronous res

LIBRARY ieee ;
ENTITY reg8 IS
PORT (
D
: IN STD_LOGIC_VECTOR(7 DOWNTO 0)
Resetn, Clock
: IN STD_LOGIC ;
Q
: OUT
STD_LOGIC_VECTOR(7 DOWNTO 0) )
END reg8 ;
ARCHITECTURE behavioral OF reg8 IS
BEGIN
8
8
Resetn
BEGIN
Q <= "00000000" ;
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
Clock
reg8
N-bit register with asynchronous reset

--Program 5.8
LIBRARY ieee ;
ENTITY regna IS
GENERIC ( N : INTEGER := 16 ) ;
PORT (
D
: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn, Clock: IN STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE behavioral OF regn IS
BEGIN

BEGIN
N
Q <= (OTHERS => '0') ;
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
Resetn N
D
Q
Clock
regn
Words on
generics
Generics are typically integer values

In this class, the entity inputs and outputs should be
std_logic or std_logic_vector
But the generics can be integer
Generics are given a default value
This value can be overwritten when entity is
instantiated as a component
Generics are very useful when instantiating an oftenused component
Need a 32-bit register in one place, and 16-bit register
in another
Can use the same generic code, just configure them
differently
Use of OTHERS
OTHERS stand for any index
value that has
not been previously mentioned.
Q <= 00000001
can be written as
Q <= (0 => 1, OTHERS => 0)
Q <= 10000001
can be written as
Q <= (7 => 1, 0 => 1, OTHERS => 0)

or
Q <= (7 | 0 => 1, OTHERS => 0)
Q <= 00011110
can be written as
Q <= (4 downto 1=> 1, OTHERS => 0)
N-bit register with enable

--Program 5.9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg_withenable IS
GENERIC ( N : INTEGER := 8 );
PORT ( D
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Enable, Clock: IN STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) );
END shiftreg_withenable;
ARCHITECTURE behavioral OF shiftreg_withenable IS
BEGIN
PROCESS (Clock)
BEGIN
N
IF (rising_edge(Clock)) THEN
IF (Enable = '1) THEN
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END behavioral ;
Enable
Q
D
Clock
regn
2-bit up-counter with synchronous reset

--Program 5.10
LIBRARY ieee ;
USE ieee.std_logic_unsigned.all ;
--
provides unsigned numerical
computation on type std_logic_vector
ENTITY upcount IS
PORT ( Clear, Clock: IN
Q
: OUT
END upcount;
STD_LOGIC;
STD_LOGIC_VECTOR(1 DOWNTO 0));
ARCHITECTURE behavioral OF upcount IS

SIGNAL Count : std_logic_vector(1 DOWNTO 0)5;
BEGIN
upcount: PROCESS (Clock)
BEGIN
IF Clear = '1' THEN
Count <= "00";
ELSE
Count <= Count + 1;
END IF;
END IF;
END PROCESS;
Q <= Count;
END behavioral;
Clear
upcount
Clock
Non-synthesizable VHDL
Delays
Delays are not synthesizable
Statements, such as
wait for 5 ns
a <= b after 10 ns
will not produce the required delay, and
should not be used in the code intended
for synthesis.
Initializations
Declarations of signals (and variables)
with initialized values, such as
SIGNAL a : STD_LOGIC := 0;
cannot be synthesized, and thus should
be avoided.
If present, they will be ignored by the
synthesis tools.
Use set and reset signals instead.
Dual-edge triggered register/counter (1)

In FPGAs register/counter can
change only at either rising (default)
or falling edge of the
clock.
Dual-edge triggered clock is not
synthesizable correctly, using either
of the descriptions provided below.

PROCESS (clk)
BEGIN
IF (clkEVENT AND clk=1 ) THEN
counter <= counter + 1;
ELSIF (clkEVENT AND clk=0 ) THEN
END IF;
END PROCESS;

PROCESS (clk)
BEGIN
IF (clkEVENT) THEN
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
END PROCESS;
Shift register internal structure
Sin
Clock
Enable
Q(1)
Q(2)
Q(3)
Q(0)
Shift Register With Parallel Load

Load
D(3)
D(1)
D(2)
Sin
D
D(0)
Clock
Enable
Q(3)
Q(2)
Q(1)
Q(0)
4-bit shift register with parallel load (1)

4
Enable
D
Q
Load
Sin
--Program 5.11
LIBRARY ieee ;
USE ieee.std_logic_arith.all ;
ENTITY shift4 IS
PORT (
Enable
Load
Sin
Clock
Q
END shift4 ;
D
:
:
:
:
:
IN
IN
IN
IN
OUT
shift4
Clock
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
4-bit shift register with parallel load (2)

4
Enable
D
Q
Load
Sin
shift4
Clock
ARCHITECTURE behavioral OF shift4 IS
SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (Clock)
BEGIN
IF Enable = 1 THEN
IF Load = '1' THEN
Qt <= D ;
ELSE
Qt <= Sin & Qt(3 downto 1);
END IF ;
END PROCESS ;
Q <= Qt;
END behavioral ;
N-bit shift register with parallel load (1)

--Program 5.12
LIBRARY ieee ;
ENTITY shiftn IS
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable : IN
STD_LOGIC ;
Load
: IN
STD_LOGIC ;
Sin
: IN
STD_LOGIC ;
Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
N
Enable
D
Q
Load
Sin
Clock
shiftn
N-bit shift register with parallel load (2)

N
Enable
D
Q
ARCHITECTURE behavioral OF shiftn IS

SIGNAL Qt: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Load
BEGIN
Sin
PROCESS (Clock)
BEGIN
Clock
IF Enable = 1 THEN
shiftn
IF Load = '1' THEN
Qt <= D ;
ELSE
Qt <= Sin & Qt(N-1 downto 1);
END IF ;
END IF;
END IF ;
END PROCESS ;
Q <= Qt;
END behavior al;
Behavioral Style ( State Table / State Diagram )
2-115
2-116
Data Flow Style ( State Equation & output Equ )
2-117
Structural Style ( Final Design (FF & Gates) )
Structural Style ( Final Design (FF & Gates) )
VHDL
Assert
- Loop
Agenda
Assert statement
Examples
Not all constructs

synthesizable
Examples given here
are just to give idea
about the syntax.
The assert statement

Assert Statement
Used for reporting, when a condition is FALSE .
Syntax
assert condition
--if condition is false
report message
--then report is printed
severity level;
--4 types of severity
TheASSERT statementserves as anexception handlingwithin a
program
and
is
most
often
used
for
test
purposes.
If the condition followingASSERTis evaluated tofalse, the default
message"Assertion
violation"is
printed.
By
means
of
theREPORTstatement, a self defined fault message can be printed by
presenting
a
text,
which
must
be
astring.
Look at where the semi-colon is placed
The assert statement
Severity level[helps to classify messages into

proper categories] is one of
Note
used as a message for debugging
Warning
for timing violations , invalid data
Error
error in the behavior of the model
Failure
catastrophic failure . simulation is halted .
Assert is both a sequential as well as a
concurrent statement
architecture beh of example is

begin
assert ( not (a = 1 and b = 1) )
report a and b cannot be
asserted at the same time
severity error;
process (din)
variable last_time : time := 0;
begin
assert ( now - last_time > 5 )
report spike on din
severity warning;
last_time := now;
end process;
end beh;
The loop statement

The continuous loop
Syntax :
[label:] [iteration_scheme] loop
statements;
end loop [loop_label];
ALOOP statementconsists of aloop header/iteration schemebefore
the
key
wordLOOPand
aloop
bodywhich
appears
betweenLOOPandEND LOOP. The loop header determines whether it
concerns theindefinitely loop,conditioned looporcounted loop. The
loop
body contains a list of statements to be executed in each iteration.
[n be
Loop
WHILE condition
FOR loop_parameter_specification
--indefinite Loop
--Conditioned Loop
--Counted Loop
The while loop
The While loop
Syntax:
[label]: while condition loop
statements;
end loop [label];
Statements are executed continuously as long
as condition is TRUE
The statements within the body of the loop are
executed sequentially
Condition is evaluated BEFORE execution.
Write a description to generate a pulse train whenever stop = 0. The
frequency of the pulse train should be half the clock frequency.
The while loop

Test_P : process
begin
. . .
Pulse_gen : while stop = 0 loop
wait until clkevent and clk = 1;
trigger <= not(trigger);
end loop pulse_gen;
. . .
end process;
The for loop

Syntax
[label]: for loop_parameter in range loop
statements;
end loop [label];
The loop parameter is implicitly defined.
The loop parameter cannot be changed inside the loop
The loop parameters scope is limited to the loop.
Write a description to initialize an array of N vectors (at reset), such
that the array holds 0, 1, .. N.
The for loop contd.

process(clk, reset)
begin
if reset = 1 then
init_loop : for i in 0 to N loop
my_array(i) <= conv_to_vector(i);
end loop;
elsif (clkevent and clk = 1) then
. . .
end process;
The for loop contd.

The loop parameter can have any discrete range
type states is (S_idle, S_wait, S_rx ...);

. . . - Enumerated data types
for st in states loop
if (st = S_idle)
do something;
-- VHDL statements
elsif(st = S_wait) then
do something;
-- VHDL statements
end if;
end loop;
The for loop contd.

Parameter range is tested before execution
labels should be used for nested loops.
a next statement can be used to skip the current iteration
and go to the next
Syntax : next [label] [when condition]
an exit statement is used to quit execution of the loop
Syntax : exit [label] [when condition]
Next and exit can be used with WHILE loop

also
The Indefinite Loop
To prevent simulation hang-up an infinite loop should usually

contain at least onewaitorexitstatement:
process (A)
variable I : integer range 0 to 4;
begin
Z <= "0000";
I := 0;
L1: loop
exit L1 when I = 4;
if (A = I) then Z(I) <= '1';

end if;
I := I + 1;
end loop;
end process;
The exit statement

process
variable count : natural := 0;
begin
count := 0;
RxLoop: while count < 255 loop
if (rx = 0) then
exit RxLoop;
end if;
if (inbyte /= FILLER) then
data(count) <= inbyte;
count := count + 1;
end if;
end loop RxLoop;
end process;
The exit statement

Conditional exit
process
begin
count := 0;
RxLoop: while count < 255 loop
exit RxLoop when (rx = 0);
if (inbyte /= FILLER) then
count := count + 1;
end if;
end loop RxLoop;
end process;
The next statement

process
begin
count := 0;
RxLoop: while rx = 1 loop
if inbyte = FILLER then
next rxloop;
end if;
count := count + 1;
exit RxLoop when (count = 255);
end loop RxLoop;
end process;
The next statement

process
begin
RxLoop: while rx = 1 loop
wait until clk = 1;
next rxloop when inbyte = FILLER;
count := count + 1;
exit RxLoop when (count = 255);
end loop RxLoop;
wait until clk = 1;
count := 0;
end process;
VHDL
Generate
- Subprograms
Array
Agenda
Generate statement
if
For
Subprograms
Procedure
function
Array
Not all constructs

synthesizable
Examples given here
are just to give idea
about the syntax.
The generate statement

generate is a concurrent statement
generate is a statement which is used to iteratively or conditionally generate
logic.
It is useful to replicate identical structures in VHDL.
generate_label : generation_scheme GENERATE

compulsory
concurrent_statement
END GENERATE generate_label ;
FOR generate_parameter_specification
IF condition
--Label is

begin
gen_loop: for i in 0 to 7 generate
port map (I(i) => a(i),
J(i) => b(i),
eq (i) => is_equal(i) );
end generate;
. . .
end my_arch_A;
Now use a generate for loop to generate a PIPO register having

clk,rst,din[3:0] and qout[3:0].

architecture GEN of REG_BANK is
component REG
port(D,CLK,RESET : in std_ulogic; Q : out
std_ulogic);
end component;
begin
GEN_REG: for I in 0 to 3 generate
REGX : REG port map
(din(I), CLK, RESET, qout(I));
end generate GEN_REG;
end GEN;
Conditional generation
if condition generate
-- concurrent statement
end generate;
Note that for generate and if generate both are concurrent
statements. So any combination is allowed.
This is usually used within afor ..generatestatement, to account for
irregularity.
U0
Sin
D
clk
U1
D
clk
U2
D
clk
Un
Reset
Sout
clk
Clock
for i in 0 to N generate
if (i = 0) generate
U: dff port map (sin , clk,
reset ,tmp(i+1));
end generate;
if ((i > 0 ) and (i < N)) generate
U: dff port map (tmp(i), clk,
reset,tmp(i+1));
end generate;
if (i = N) generate
U: dff port map (tmp(i), clk,
reset, sout);
end generate;
end generate;
Write a VHDL code for a 4 bit ripple-carry adder with no carry-in
Subprograms
Subprograms consist of procedures and functions
A function can return only one argument; a procedure
can return more than one arguments.
In a function all parameters are input parameters. In a
procedure parameters can be input, output or inout.
Subprograms can be concurrent or sequential.
Subprograms can have only sequential statements.
Subprograms can have any sequential statement,
including the wait statement.
The procedure exists as a separate statement in the
architecture or process, while the function is a part of
an expression.
Subprograms
Subprograms can be defined either in a
package, architecture or process.
Avoid subprogram side-effects.
Signal type of attributes cannot be used within
a subprogram.
A return statement in a function has a return
expression whereas the procedure return
statement does not have an expression.
The procedure statement

A procedure is subroutine which performs operations
using all the parameters and objects, and which can
change one or more of the parameters and objects in
accordance with rules governing those parameters and
objects.
A concurrent procedure has an implied wait statement
at the end of the procedure on the signals whose mode
has been declared as IN or INOUT.
A sequential procedure has no implied wait.
A sequential procedure which uses wait statements
cannot be called from a process with sensitivity list.
Procedure statement may or may not be executed on
zero simulation time. ( depend on it has Wait statement)
Syntax
procedure <procedure_name> ( parameter list ) is
declarations;
begin
statements;
end [ procedure ] [ name] ;
function <function_name> ( parameter list )
return <return_type> is
declarations;
begin
statements;
return parameter;
end [ function ] [ function_name ];
Parameter list
Parameter list specification consists of:
Class definition (signal, variable, constant).
Name of the parameter.
Mode of the parameter (in, out, inout).
Subtype indication.
Optional initial value.
Class constant is assumed if an interface class is
not specified
For procedures always specify the mode of the
parameters (in, out, inout). For functions all
parameters are of mode in and hence need not be
specified.
Parameter list
Parameters passing
Signals can only be associated with signals
Variables can only be associated with variables.
Constants can be associated with either signal,
variable or constant
A parameter cannot have an initialization value if it
is a signal or if it has a mode other than IN.
The actual value of the parameter passed overrides
the default value.
The actual signal associated with a signal
parameter must be static.
The procedure statement contd.

Write a procedure to calculate the parity of the bits of
the vector variable (7:0) passed to it.
procedure parity(
variable din : std_logic_vector(7 downto 0);
variable parity_out : out std_logic
) is
variable temp : std_logic;
begin
temp := 0;
for i in 7 downto 0 loop
temp := temp exor din(i);
end loop;
parity_out := temp;
end parity;
The procedure statement contd.

Write a procedure to calculate the Average of 256
number stored in some my _list. Where my_list is user
defined type
Example
procedure avg_samples(signal samples: in my_list;
signal average: out real) is
variable total: real := 0.0;
begin
for index in 0 to 255 loop
total := total + samples(index);
end loop;
average <= total/256.0;
end procedure avg_samples;
signal data_in_list : my_list;
signal average_value : real;
begin
. . .
avg_samples(data_in_list, average_value);
The function statement

Unlike procedure a function cannot change its
argument and can only return a value.
Function parameters default class is constant.
A function has to have a return statement with
an expression . The value of the expression
defines the result returned by the function.
Parameters of a function may not be of class
variable.
Executed in Zero simulation time
The function statement contd.
function name (parameter_list) return type is

declarations
begin
statements
return (expression);
end name;
Write a function to calculate the parity of

the bits of the vector (7:0) passed to it.

function parity(
signal din: std_logic_vector(7 downto 0);
)
return std_logic is
variable temp : std_logic;
begin
temp := 0 ;
for i in 7 downto 0 loop
temp := temp exor din(i);
end loop;
return (temp);
end parity;
process (Bdata)
begin
Bparity <= parity(Bdata);
end process;
Function as data Type conversion:

An Example
The function statement as type conversion

function TO_CHARACTER (ARG : STD_ULOGIC)
return CHARACTER is
begin
case ARG is
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
end case;
end TO_CHARACTER
Side effects
A sub program is said to have side effects if it
changes something not declared in its parameter
list.
Procedures and impure functions (VHDL93)
defined in the architecture have visibility of the
ports and the signals declared in the
architecture.
They have visibility of the variables and loop
parameters in the calling process.
They also have visibility to the global signals.
Avoid side effects on procedures. If it is
unavoidable then comment it properly.
ROM
Instruction ROM example (1)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY instruction_rom IS
0);
GENERIC ( w : INTEGER := 16;

n : INTEGER := 8;
m : INTEGER := 3);
PORT (
Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO
Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0)
);
END instruction_rom;
Instruction ROM example (2)

ARCHITECTURE ins_rom OF instruction_rom IS
SIGNAL temp: INTEGER RANGE 0 TO n-1;
TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1
DOWNTO 0);
CONSTANT memory : vector_array :=
(
X"0000",
X"D459",
X"A870",
X"7853",
X"650D",
X"642F",
X"F742",
X"F548");
BEGIN
temp <= to_integer(unsigned(Instr_addr));
Instr <= memory(temp);
END instruction_rom;
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VHDL

Sequence of the statements is important as in

HDL Implementation Design Cycle

Advantage of Using Hardware Description

Early Testing of Various Design Implementations

Due to fast synthesis, there is a scope for trying different implementations.

Technology independence, standardization, portability, ease of maintenance.

VHSIC (Very High Speed Integrated Circuit)

architecture my_exor_beh of my_exor is

architecture my_exor_beh of my_exor is

Internal connections are made using signals.

my EXOR with internal

Other VHDL resources

VHDL Tutorial: Learn by Example

Well, not EVERYTHING ... :)

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Register Transfer Logic (RTL) Design

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my EXOR with internal

A specified port should have a self explanatory name that

Driver may reside both

Output port with internal read capability

An architecture specifies the behavior, function, interconnections and the

An entity can have more than one architecture .

Each architecture is bound to an entity using the configuration

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VHDL Architecture Design Styles

Subset most suitable for synthesis

VHDL Arch 4 ways of doing it

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Architecture- An intuitive way

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1 bit Half Adder

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1 bit Half Adder- Behavioral

Concurrent signal assignment

Conditional concurrent signal assignment

Selected concurrent signal assignment

Generate scheme for equations

1 bit Half Adder- Data Flow

like Boolean Equation

<= is concurrent Assignments

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1 bit Half Adder- Structural

1 bit Half Adder- Strutural

1 bit Half Adder- Structural

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1 bit Full Adder

1 bit Full Adder- Behavioral

If the state is Waiting, a condition

WAIT statement Syntax

The wait statement causes the suspension of a process

Condition_clause ::= until boolean_expression

Timeout_clause ::= for time_expression

Example to test the wait until

Sensitivity-lists vs Wait-on statement

Differences between signals and variables

Sum1 and sum2 are signals

end case [ case _label ];

Conditional concurrent signal

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