FPGA ARCHITECTUTE

Programmable Logic
Programmable Logic Devices (PLDs) are chips with a large number of gates and
flip flops that can be configured with software to perform a specific logic function
:or perform the logic for a complex circuit. Major types of PLDs are

SPLD (Simple PLD): the earliest type of array logic used for
fixed functions and smaller circuits with a limited number of
gates. (The PAL and GAL are both SPLDs).
CPLD (Complex PLD): contain multiple SPLD arrays and interconnection arrays on a single chip.
FPGA (Field Programmable Gate Array): a more flexible
arrangement than CPLDs, with much larger capacity.

Floyd, Digital Fundamentals,

10th ed

Pearson Education, Upper Saddle River, NJ 07458. All 2009

Rights Reserved

Programmable Logic
Advantages of PLDs over fixed-function chips include
Reduced complexity of circuit boards
Lower power requirements
Less board space
Simpler testing procedures
Higher reliability
Design flexibility

Floyd, Digital Fundamentals,

10th ed

Pearson Education, Upper Saddle River, NJ 07458. All 2009

Rights Reserved

PALs and GALs

All PLDs contain arrays. Two important kinds of SPLD are PALs
(Programmable Array Logic) and GALs (Generic Array Logic). A typical
array consists of a matrix of conductors connected in rows and columns
to AND gates.
PALs have a one-time
programmable (OTP)
array, in which fuses are
permanently blown,
creating the product
terms in an AND array.

A
B

Simplified AND-OR
array
Floyd, Digital Fundamentals,
10th ed

Pearson Education, Upper Saddle River, NJ 07458. All 2009

Rights Reserved

GALs
The GAL (Generic Array Logic) is similar to a PAL but can be
reprogrammed. For this reason, they are useful for new product
development (prototyping) and for training purposes.
A

GALs were developed by

Lattice Semiconductor.
X

Floyd, Digital Fundamentals,

10th ed

Pearson Education, Upper Saddle River, NJ 07458. All 2009

Rights Reserved

CPLDs
A complex programmable logic device (CPLD) has multiple logic array
blocks (LABs), each roughly equivalent to an SPLD. LABs are
connected via a programmable interconnect array (PIA). Various
CPLDs have different structures for these elements.
The PIA is the interconnection
between the LABs.
I/O

I/O

I/O

Floyd, Digital Fundamentals,

10th ed

Logic array
block (LAB)

Logic array
block (LAB)

SPLD

SPLD

Logic array
block (LAB)

PIA

Logic array
block (LAB)

SPLD

SPLD

Logic array
block (LAB)

Logic array
block (LAB)

SPLD

SPLD

I/O

I/O

I/O

Pearson Education, Upper Saddle River, NJ 07458. All 2009

Rights Reserved

Architecture of Field Programmable Gate Arrays (FPGA)

- It is consisting of an array of logic blocks that
can be programmable interconnected to realize
different designs
- FPGA is programmed via electrically
programmable switches much the same as
traditional programmable logic devices (PLDs).
- FPGAs can be used to implement just about
any hardware design.
- The common feature of these is that FPGA is a set
of free or semi-free connection matrix gates.
- FPGA logic blocks differ greatly in their size and implementation capability. This logic
can be very small as two-transistor logic block used in the Crosspoint FPGA and can be
significantly of large size like the look-up table used in the Xilinx 3000 series FPGA.

 Inexpensive, easy realisation of logic

networks in hardware
Hardware of FPGAs contains:
Plds
Logic gates
Ram
Layout of a unit is reapeated in matrix form
User configure
Function of each logic block
IOB
Interconnections

Programming Technologies
1- SRAM Programming Technology
- FPGA connections are
achieved using pass-transistors,
transmission gates, or
multiplexers that are controlled
by SRAM cells
- It is used in the devices from Xilinx , Altera, Plessey,
Algotronix, Concurrent Logic and Toshiba.
Disadvantage:
Its large area. It takes at least five transistors to implement an SRAM cell, plus at
least one transistor to serve as a programmable switch.
Advantages:
1- fast re-programmability (The FPGA can be programmed an unlimited number
of times)
2- It requires only standard integrated circuit process technology.

Antifuse Programming Technology- 2

- Antifuse is a two terminal device with an
unprogrammed state presenting a very high
resistance between its terminals.
- When a high voltage (from 11 to 20 volts,
depending on the type of antifuse) is applied
across its terminals the antifuse will blow
and create a low resistance link
- Antifuse technology is used in the FPGAs from Actel, Quicklogic, and Crosspoint.
Advantages:
1- Its small size. This advantage is somewhat reduced by the large size of the
necessary programming transistors, which must be able to handle large currents, and
the inclusion of isolation transistors that are sometimes needed to protect low
voltage transistors from high programming voltages.
2- A second major advantage of an antifuse is its relatively low series resistance.
Disadvantage:
This technology can be used only once on one-time programmable (OTP) devices

Floating Gate Programming Technology- 3

- The floating gate programming (or
EPROM/E2PROM ) technology uses technology
found in ultraviolet erasable EPROM and
electrically erasable E2PROM devices. It is used
in devices from Altera and Plus Logic.
- The programmable switch is a transistor that can be permanently disabled. This
is accomplished by injecting a charge on the floating gate (gate 2 in the Figure)
using a high voltage between the control gate 1 and the drain of the transistor. This
charge increases the threshold voltage of the transistor so that it turns off.
Advantages:
1-its re-programmability.
2- No external permanent memory (like in SRAM) is needed to program the chip on
power-up.
Disadvantage:
An E2PROM cell is roughly twice the size of an EPROM cell

Logic Block Architecture

Fine-Grain Logic Blocks

1- The Crosspoint FPGA

- The FPGA from Crosspoint solutions
uses a single transistor pair in the logic
block
- Since the transistors are connected
together in rows, the two two-input
NAND gates are isolated by turning off
the pair of transistors between the gates

The Plessey FPGA-2

- The main advantage of using
fine grain logic blocks is that the
useable blocks are fully
utilized. This is because it is
easier to use small logic gates
efficiently.
- The main disadvantage of fine
grain blocks is that they require a
relatively large number of wire
segments and programmable
switches. Such routing resources
are costly in delay and area.

Coarse-Grain Logic Blocks

Actel Logic Block- 1
Act-1

logic functions can be realized 702

Act-2

logic functions can be realized 766

- the 16-bit adder needs about 3000 Actel-2 logic block

with each block having 14 transistors. Hence, it needs
about 42,000-transistor.

The Altera Logic Block- 3

- The architecture of the Altera
FPGA has evolved from the
PLA-based architecture of
traditional PLDs with its
logic block consisting of wide
(20 to over 100 inputs) AND
gates feeding into an OR gate
with three to eight inputs.

The Altera 5000 Series logic block

- The advantage of this type of block is that the wide AND gate can be used to form
logic functions with few levels of logic blocks, reducing the need for programmable
interconnect. As well as logic connections also serve as the routing function.
- A disadvantage of the wired-AND configuration is the use of pull-up devices
that consume static power. An array full of these pull-ups will consume
significant amount of power. To mitigate this, each gate in the MAX 7000 series
block can be programmed to consume about 60% less power but at the expense of
about 40% increase in delay.

The Xilinx Logic Block-4

- The basis for the
Xilinx logic block is
an
SRAM
functioning as a
look-up table (LUT).
The truth table for a
K-input
logic
function is stored in
a2 K 1
SRAMof
- The advantage
the look-up tables
is that they exhibit
high
functionality, a Kinput LUT that can
implement
any
function of K inputs
and
K there are
22
such
functions

The Xilinx 3000 logic block

Lookup table-based logic

LUT inputs
PROM bits
required
Possible functions

Generall
y
nn

2
22

For 4-input LUT For 5-input LUT

4
16

5
32

16

65,536

32

4,294,967,296

- Its disadvantage is that they will be quite large for more than
about five inputs, since the number of memory cells
K needed for a
2
K-input LUT is

FPGA Generic Design Flow

First step is the Design entry
That means we create design using
Schematic or HDL.
Second step is to implementation of the
design
It undergoes three steps
Partitioning
Place
Routing
Third step is the Verification
Uses simulator to check functionality

FPGA Generic Design Flow

Design Entry: creation of design
files using schematic editor or
hardware description language
Design Synthesis: creation of a
lower level of logic abstraction
using a library of primitives.
Partition
(or
Mapping):
assigning to each logic element a
specific physical element
Place: maps logic into specific
locations in the target FPGA chip.
Route: connections of the mapped logic.
Program Generation: a bitstream file is generated to
program the device.
Device
Programming:
downloading the bit-stream to
the FPGA.
Design Verification: simulation is used to check
functionalities

FPGAs compared to CPLDs

CPLDs

FPGAs

Based on
programmable AND
array and fixed OR
.array

Based on look-up table

(LUT), which is basically
a truth table. (Results
in higher density.)

Usually EEPROM
Usually SRAM
technology, so non.technology, so volatile
.volatile
Both are programmed using the same software,
.using either schematic entry or text entry