Chapter 5.1-5.2
Von Neumann
Architecture
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(c) Yngvi Bjornsson
Designing Computers
CMPUT101
Introduction to
Computing
3
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CMPUT101
Introduction to
Computing
Memory
ALU (Arithmetic/Logic Unit)
Control Unit
Input/Output System (I/O)
Control Unit
ALU
Input-Output
Communicate with
"outside world", e.g.
Screen
Keyboard
Storage devices
...
(c) Yngvi Bjornsson
5
(c) Yngvi Bjornsson
CMPUT101
Introduction to
Computing
Subsystem
Memory
Memory, also
called RAM (Random Access Memory),
Consists of many memory cells (storage units) of a fixed
size.
Each cell has an address associated with it: 0, 1,
All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a
complete cell).
The time it takes to fetch/store a cell is the same for all
cells.
RAM
CMPUT101
Introduction to
Computing
0000000000000001
0
1
2
1 bit
2N
...
2N-1
CMPUT101
Introduction to
Computing
Memory sizes:
Kilobyte (KB) = 210 =
1,024 bytes ~ 1 thousand
Megabyte(MB) = 220 =
1,048,576 bytes ~ 1 million
Gigabyte (GB) = 230 = 1,073,741,824 bytes ~ 1 billion
RAM is
volatile (can only store when power is on)
relatively expensive
Operations on Memory
CMPUT101
Introduction to
Computing
Fetch (address):
Fetch a copy of the content of memory cell with the
specified address.
Non-destructive, copies value in memory cell.
MDR
F/S
Memory
decoder
circuit
Fetch/Store
controller
Fetch(address)
Load address into MAR.
Decode the address in MAR.
Copy the content of memory cell
with specified address into
MDR.
Store(address, value)
...
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(c) Yngvi Bjornsson
CMPUT101
Introduction to
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Input/Output
Handles devicesSubsystem
that allow the computer
system to:
11
I/O Controllers
CMPUT101
Introduction to
Computing
Solution:
12
CMPUT101
Introduction to
Computing
I/O controller
I/O Buffer
Control/Logic
I/O device
13
CMPUT101
Introduction to
Computing
ALU circuitry:
R0
R1
R2
Rn
ALU circuitry
Bus:
Data path interconnecting the
registers to the ALU circuitry.
CMPUT101 Introduction to Computing
GT EQ LT
(c) Yngvi Bjornsson
14
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CMPUT101
Introduction to
Computing
The
Control
Unit
Program
is stored
in memory
as machine language instructions, in binary
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CMPUT101
Introduction to
Computing
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(c) Yngvi Bjornsson
CMPUT101
Introduction to
Computing
18
(c) Yngvi Bjornsson
CMPUT101
Introduction to
Computing
Typical
Machine Instructions
Notation:
We use X, Y, Z to denote RAM cells
Assume only one register R (for simplicity)
Use English-like descriptions (should be binary)
STORE X
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CMPUT101
Introduction to
Computing
Arithmetic
Compare
COMPARE X, Y
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CMPUT101
Introduction to
Computing
memory loc. X
JUMPGT X
Control
HALT
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Example
CMPUT101
Introduction to
Computing
Pseudo-code: Set A to B + C
Assuming variable:
A stored in memory cell 100, B stored in
memory cell 150, C stored in memory cell 151
LOAD
ADD
STORE
or
(ADD
150
151
100
150, 151, 100)
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CMPUT101
Introduction to
Computing
PC (Program Counter):
stores the address of next instruction to fetch
IR (Instruction Register):
stores the instruction fetched from memory
Instruction Decoder:
Decodes instruction and activates necessary
circuitry
PC
+1
IR
Instruction
Decoder
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(c) Yngvi Bjornsson
CMPUT101
Introduction to
Computing
von Neumann
Architecture
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CMPUT101
Introduction to
Computing
End of loop
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CMPUT101
Introduction to
Computing
Program
Execution
(cont.)
Fetch phase
PC --> MAR
Fetch signal
MDR)
MDR --> IR
PC + 1 --> PC
Decode Phase
IR -> Instruction decoder (decode instruction in IR)
Instruction decoder will then generate the signals to
activate the circuitry to carry out the instruction
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CMPUT101
Introduction to
Computing
Example:
LOAD X (load value in addr. X into register)
IR_address -> MAR
Fetch signal
MDR --> R
ADD X
left as an exercise
27
0000
0001
0010
0011
0100
0101
0101
LOAD X
STORE X
CLEAR X
ADD X
INCREMENT X
SUBTRACT X
DECREMENT X
COMPARE X
CON(X) --> R
R --> CON(X)
0 --> CON(X)
R + CON(X) --> R
CON(X) + 1 --> CON(X)
R - CON(X) --> R
CON(X) - 1 --> CON(X)
JUMP X
JUMPGT X
JUMPxx X
IN X
OUT X
HALT
0111
1000
1001
...
1101
1110
1111
CMPUT101
Introduction to
Computing
Lecture 1
Von Neuman Architecture
Review Agenda
Von
Neumann Architecture
Design
Bus
Control
Main
Memory
Computer
Input
Device
Data
CPU
Bus
Main
Memory
Output
Device
Control
Five Main Components:
1. CPU
2. Main Memory (RAM)
3. I/O Devices
4. Mass Storage
5. Interconnection network (Bus)
Bus
Bus
Secondary
Storage
Device
Instruction Cycle
Basic
Intermediate
Exceptions
Start
Fetch
Instruction
Execute
Instruction
complete instruction
consists of
operation code
addressing mode
zero or more operands
immediately available data
(embedded within the
instruction)
the address where the data
can be found in main
memory
Fetch
Instruction
Decode
Instruction
Fetch
Operand
Execute
Instruction
Start
Possible
Exception?
Fetch
Instruction
Possible
Exception?
Decode
Instruction
Possible
Exception?
Fetch
Operand
Possible
Exception?
Execute
Instruction
Start
Fetch
Instruction
Decode
Instruction
Fetch
Operand
Execute
Instruction
Start
Fetch
Instruction
Decode
Instruction
Fetch
Operand
Execute
Instruction
Start
Fetch
Instruction
Decode
Instruction
Fetch
Operand
Execute
Instruction
Instruction Architecture
Software
design
Hardware circuits
Each computer CPU must be designed to accommodate and understand instructions according to
specific formats.
Examples:
OpCode
Each computer CPU must be designed to accommodate and understand instructions according to
specific formats.
Examples:
OpCode
Operand (Address)
Sometimes the instruction format requires a code, called the Mode, that specifies a particular addressing format to be distinguished from
other possible formats
direct addressing
indirect addressing
indexed addressing
relative addressing
etc.
OpCode
Mode
Op. (Addr.)
Mode
Op. (Addr.)
I/O 2
I/O n
System Bus
CPU
RAM
System Bus
CU
IR
Internal
CPU Bus
PSW
Address Bus
PC
Data Bus
Regs
Control Bus
ALU
At
ALL
We
All
Instruction Architecture - CU
The
Each
It
CISC
RISC
Each