Overview
Memory definitions
Random Access Memory (RAM)
Static RAM (SRAM) integrated circuits
Cells and slices
Cell arrays and coincident selection
Memory Definitions
Memory A collection of storage cells together with
the necessary circuits to transfer information to and
from them.
Memory Organization the basic architectural
structure of a memory in terms of how data is accessed.
Random Access Memory (RAM) a memory
organized such that data can be transferred to or from
any cell (or collection of cells) in a time that is not
dependent upon the particular cell selected.
Memory Address A vector of bits that identifies a
particular memory element (or collection of elements).
Chapter 8 3
Memory Organization
Organized as an indexed array of words. Value of the
index for each word is the memory address.
Often organized to fit the needs of a particular
computer architecture. Some historically significant
computer architectures and their associated memory
organization:
Digital Equipment Corporation PDP-8 used a 12-bit address
to address 4096 12-bit words.
IBM 360 used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
Intel 8080 (8-bit predecessor to the 8086 and the current
Intel processors) used a 16-bit address to address 65,536 8-bit
bytes.
Chapter 8 5
k
1
Memory
Unit
2k Words
n Bits per Word
1
n
Chapter 8 6
Memory Address
Binary Decimal
000
001
010
011
100
101
11 0
111
0
1
2
3
4
5
6
7
Memory
Content
10001111
11111111
10110001
00000000
10111001
10000110
00110011
11001100
Chapter 8 7
20 ns
T1
T2
T3
T4
T1
Address valid
Memory
enable
Read/
Write
Data
output
Data valid
65 ns
Read cycle
Chapter 8 10
20 ns
T1
T2
T3
T4
T1
Address valid
Memory
enable
Read/
Write
Data
input
Data valid
75 ns
Write cycle
Q
RAM cell
Chapter 8 13
Word
select
0
Word
select
0
RA M cell
RA M cell
Word
select
1
RA M cell
Select
Word
select
2n 2 1
Data Lines:
Data in
Data out
Word
select
2n 2 1
RA M cell
X
RA M cell
Read/Write
logic
Data in
Data in
Data out
Read/
Bit
Write
select
(b) Symbol
Write logic
Read/
Write
Bit
select
Read logic
(a) Logic diagram
Data out
Chapter 8 14
A3
A3
A2
A2
A1
A1
A0
16 x 1
RAM
Data
output
Data
input
A 3-state buffer
Read/
Write
on the data output Memory
permits RAM ICs to enable
be combined into a
RAM with c 2n words
A0
Word select
4-to-16
Decoder 0
1
23
2
RAM cell
2
3
2
4
1
5
2
6
RAM cell
0
7
2
8
9
10
11
12
13
14
15
RAM cell
Read/Write
logic
(a) Symbol
Data input
Data in
Data out
Read/ Bit
Write select
Data
output
Read/Write
Chip select
Chapter 8 15
Row decoder
2-to-4
Decoder 0
21
A2
20
RAM cell
0
RAM cell
1
RAM cell
2
RAM cell
3
RAM cell
5
RAM cell
6
RAM cell
7
RAM cell
8
RAM cell
9
RAM cell
10
RAM cell
11
RAM cell
12
RAM cell
13
RAM cell
14
RAM cell
15
Read/Write
logic
Read/Write
logic
Read/Write
logic
Read/Write
logic
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data input
Read/Write
X
Column select
0
A0
Data
output
Enable
Chip select
Chapter 8 17
Row decoder
2-to-4
Decoder 0
21
A1
20
RAM cell
0
RAM cell
1
RAM cell
2
RAM cell
3
RAM cell
5
RAM cell
6
RAM cell
7
RAM cell
8
RAM cell
9
RAM cell
10
RAM cell
11
RAM cell
12
RAM cell
13
RAM cell
14
RAM cell
15
Read/Write
logic
Read/Write
logic
Read/Write
logic
Read/Write
logic
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data input 0
Data input 1
Read/Write
Column select
0
1
1-to-2
Decoder
Column
decoder with enable
Enable
20
A0
Data
Output 0
Chip select
Data
Output 1
Chapter 8 19
A0
R/W
Decoder
Data In
D3
A1 D-In
A0
R/W
CS D-Out
D2
A1 D-In
A0
R/W
CS D-Out
D1
A1 D-In
A0
R/W
CS D-Out
S1 D0
S0
A1 D-In
A0
R/W
CS D-Out
Data Out
Chapter 8 20
Data In
3210
A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out
CS
Data Out
3210
Chapter 8 21
Read/ Write
2-to-4 Decoder
EN
3 2 1 0
Lines 0 -15
16
Input
Data
8
0 - 65535
64K 8 RAM
DATA
ADRS
CS
R/W
65536- 131071
64K 8 RAM
DATA
ADRS
CS
R/W
131072 - 196607
64K 8 RAM
DATA
ADRS
CS
R/W
196608 - 262143
64K 8 RAM
DATA
ADRS
CS
R/W
8
Output Data
Chapter 8 22
16
64K 8 RAM
8
16
Chip Select
Read / Write
64K 8 RAM
8
DATA
ADRS
16
CS
R/W
DATA
ADRS
CS
R/W
Chapter 8 23
Read/ Write
2-to-4 Decoder
EN
3 2 1 0
64K 8 RAM
64K 8 RAM
DATA
ADRS
CS
R/W
DATA
ADRS
CS
R/W
64K 8 RAM
64K 8 RAM
DATA
DATA
ADRS
CS
R/W
64K 8 RAM
64K 8 RAM
DATA
DATA
ADRS
CS
R/W
CS
R/W
64K 8 RAM
64K 8 RAM
DATA
DATA
ADRS
CS
R/W
ADRS
CS
R/W
ADRS
ADRS
CS
R/W
8
Chapter 8 24
C
DRAM cell
(b)
(a)
(c)
Write 1
Select
Stored 0
Stored 1
To Pump
(d)
Write 0
(e)
Read 1
Read 0
DRAM cell
model
(h)
(f)
(g)
Chapter 8 26
Word
select
0
Select
Word
select
0
DRA M cell
model
DRA M cell
Word
select
1
DRA M cell
Select
2- 1
D
2
- 1
DRA M cell
model
DRA M cell
Read/Write
logic
Sense
amplifier
Data in
Data in
Data out
Read/ Bit
Write
select
(b) Symbol
Write logic
Read/
Write
Bit
select
Read logic
Data out
Chapter 8 27
Row
Address
Row Address
Register
RAS
Row Timing
Logic
CAS
Refresh
Counter
Row Address
Register
DRAM
Bit Slice
DRAM
Bit Slice
DRAM
Bit Slice
R/W
OE
Column
Address
Row Timing
Logic
Column Decoder
Data In /
Data Out
Chapter 8 28
The column address is used to select the word to be placed on the output from the data read
from the row of cells.
The address is split to roughly halve the large number of address pins on the typical RAM IC.
Chapter 8 29
Address
T1
T2
T3
T4
T1
Column
Address
Row
Address
RAS
CAS
Output
enable
Read/
Write
Data
output
Hi-Z
Data valid
65 ns
Read Cycle
Chapter 8 30
Address
T1
Row
Address
T2
T3
T4
T1
Column
Address
RAS
CAS
Output
enable
Read/
Write
Data
output
Data valid
75 ns
Write Cycle
Chapter 8 31
DRAM Types
DRAM Types:
Synchronous DRAM (SDRAM)
Double Data Rate SDRAM (DDR SDRAM)
RAMBUS DRAM (RDRAM)
DRAM Types
Justification for effectiveness of these types (continued)
These words are then transferred out over the memory data
bus using a series of clocked transfers
These transfers have a low delay, so several can be done in a
short time
The column address is captured and used by a synchronous
counter within the DRAM to provide consecutive column
addresses for the transfers
Chapter 8 33
Synchronous DRAM
Transfers to and from the DRAM are synchronize with a clock
Synchronous registers appear on:
Address input
Data input
Data output
Chapter 8 35
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Chapter 8 38