Introduction
I/O devices serve two main purposes
To communicate with outside world
To store data
Introduction (contd)
Introduction (contd)
To communicate with an I/O device, we need
Access to various registers (data, status,)
This access depends on I/O mapping
Two basic ways
Memory-mapped I/O
Isolated I/O
Isolated I/O
Separate I/O address space
Separate I/O read and write signals are needed
Pentium supports isolated I/O
FFFFF
64 KB address space
Can be any combination of 8-, 16- and 32-bit I/O ports
Also supports memory-mapped I/O
FFFFF
Memory
addressing
space
00000
I/O
FFFF I/O
addressing
0000 space
Direct I/O
00000
Memory addressing
space
Memory-mapped I/O
accumulator, port8
; direct format
in
accumulator,DX
; indirect format
FFFF
Accessed
through
DX
00FF
00F8
Accessed
directly by
instructions
AL,
AX,
3CH,
0A0H,
80H
6H
AL
AX
Accessing through DX
IN
AL,
IN
AX,
OUT DX,
OUT DX,
DX
DX
AL
AX
0000
7
8086/88
Gating
device
Address bus
Input
Decoder
Other control
signals
The outputs of the gating device are high impedance when the processor is not
accessing the input port
When the processor is accessing the input port, the gating device transfers input
data to CPU data bus
The decoding circuit controls when the gating device has high impedance output
and when it transfers input data to data bus
8
A7
A6
A5
A4
A3
A2
A1
A0
Data bus
Tri-state
buffer
Input data
CE
RD IO/M
10
A7
A6
A5
A4
A3
A2
A1
A0
Data bus
Latch
Output data
CLK
WR IO/M
11
12
A6
A5
A=B
B3
A3
B2
A2
B1
A1
A4
A0
A7
Vcc
R
B0
A=B
A2
A1
A=B
B3
A3
B2
A2
B1
A1
A0
A0
A3
B0
A=B
RD or WR
IO/M
13
14
Port address
60H
61H
62H
63H
15
16
An end-notification phase
Programmed I/O
Interrupt
Example
Reading a key from the keyboard involves
Waiting for PA7 bit to go low
Indicates that a key is pressed
20
21
Introduction (contd)
22
23
8088
A7
A6
A5
A4
A3
A2
IO/M
D[7:0]
PA[7:0]
PB[7:0]
Control port
PC[7:0]
CS
A1
A0
0
0
1
1
0
1
0
1
Port
PA
PB
PC
Control
24
FFFF
Accessed
through
DX
00FF
00F8
Accessed
directly by
instructions
AL,
AX,
3CH,
0A0H,
80H
6H
AL
AX
Accessing through DX
IN
AL,
IN
AX,
OUT DX,
OUT DX,
DX
DX
AL
AX
0000
25
Programming 8255
8255 has three operation modes: mode 0, mode 1, and mode 2
26
Programming 8255
Mode 0:
Ports A, B, and C can be individually programmed as input or output ports
Port C is divided into two 4-bit ports which are independent from each other
Mode 1:
Ports A and B are programmed as input or output ports
Port C is used for handshaking
PC4
PC5
PC3
8255
PA[7:0]
STBA
IBFA
INTRA
PB[7:0]
PC2
PC1
PC0
PC6, 7
STBB
IBFB
INTRB
PC7
PC6
PC3
8255
PA[7:0]
OBFA
ACKA
INTRA
PB[7:0]
PC2
PC1
PC0
PC4, 5
OBFB
ACKB
INTRB
27
A7
A6
A5
A4
A3
A2
A1
A0
Data bus
Tri-state
buffer
Input data
CE
RD IO/M
28
Programming 8255
Mode 0:
Ports A, B, and C can be individually programmed as input or output ports
Port C is divided into two 4-bit ports which are independent from each other
Mode 1:
Ports A and B are programmed as input or output ports
Port C is used for handshaking
PC4
PC5
PC3
8255
PA[7:0]
STBA
IBFA
INTRA
PB[7:0]
PC2
PC1
PC0
PC6, 7
STBB
IBFB
INTRB
PC7
PC6
PC3
8255
PA[7:0]
OBFA
ACKA
INTRA
PB[7:0]
PC2
PC1
PC0
PC4, 5
OBFB
ACKB
INTRB
29
Programming 8255
Mode 2:
Port A is programmed to be bi-directional
Port C is for handshaking
Port B can be either input or output in mode 0 or mode 1
PA[7:0]
8255
PC7
PC6
PC4
PC5
PC3
PC0
PC0
PC0
OBFA
ACKA
STBA
IBFA
INTRA
In
In
In
PB[7:0]
1.
2.
Out
Out
Out
STBB
IBFB
INTRB
OBFB
ACKB
INTRB
Mode 1
Mode 0
Can you design a decoder for an 8255 chip such that its base address is 40H?
Write the instructions that set 8255 into mode 0, port A as input, port B as output,
PC0-PC3 as input, PC4-PC7 as output ?
32
8255
PA0
BIT5 EQU
PORTC
PORTA
20H
EQU
EQU
READ
Read:
PROC NEAR
IN AL, PORTC
TEST AL, BIT5
JZ Read
IN AL, PORTA
READ
22H
20H
PA7
STB
PC4
DAV
; read portc
;test IBF
;if IBF=0
;Read Data
ENDP
34
8255
PB0
PB7
ACK
PC2
ACK
PC4
DS
35
2
EQU 62H
EQU 61H
63H
NEAR
PRINT ENDP
36
Keyboard example
37
Keyboard example
38
Bouncing Problem
39
Bouncing
40
Software Solution
41
De-bouncing Circuitry
Two asynchronous flip-flop solutions are given below
The basic idea is that these flip-flops store the values even if the D/D
nodes both float
42
Another Solution
43
External Interface
Two ways of interfacing I/O devices
Serial
Cheaper
Slower
Parallel
Faster
Limited to small
distances
44
External Interface
Two basic modes of data transmission
45
External Interface
Serial transmission
Asynchronous
Each byte is encoded for transmission
Start and stop bits
Synchronous
Sender and receiver must synchronize
Block of data can be sent
More efficient
Less overhead than asynchronous transmission
Expensive
46
External Interface
47
External Interface
Asynchronous transmission
48
Data Communications
MODEMS
MODEMS
External Interface
EIA (Electronics Industries
Association) -232 serial interface
Low-speed serial transmission
Adopted by Electronics Industry
Association (EIA)
Popularly known by its predecessor
RS-232
53
External Interface
Transmission protocol uses three phases
Connection setup
Computer A asserts DTE (Data Terminal Equipment)
Ready
Transmits phone# via Transmit Data line (pin 2)
External Interface
The last two phases of Transmission
protocol
Data transmission
Connection termination
Done by deactivating RTS
55
Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication
Synchronous transfer does not transfer extra bits. However, it requires clock signal
Frame
Asynchronous
Data transfer
data
Start
bit B0 B1 B2 B3 B4
B5 B6
Stop bits
Parity
clk
Synchronous
Data transfer
data
B0
B1
B2
B3
B4
B5
Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).
56
RS232
TxD
RD
WR
A0
RD
WR
C/D
CLK
CLK
RxD
TxC
RxC
A7
A6
A5
A4
A3
A2
A1
IO/M
57
58
Low level
It is also possible to set the device in "break status" (low level) by a
command.
60
61
In "synchronous mode,"
the baud rate will be the same as the frequency of TxC
In "asynchronous mode
it is possible to select the baud rate factor by mode
instruction
It can be 1, 1/16 or 1/64 the TxC
The falling edge of TxC shifts the serial data out of the
8251
62
In "synchronous mode,"
the baud rate will be the same as the frequency of RxC
In asynchronous mode
It is possible to select the baud rate factor by mode
instruction
It can be 1, 1/16 or 1/64 the TXC
63
64
In "asynchronous mode,"
this is an output terminal which generates "high level
output
Upon the detection of a "break" character if receiver data
contains a "low-level" space between the stop bits of two
continuous characters
65
66
67
Programming 8251
8251 mode register: to initialize 8251, Mode word is to be sent followed
by command word
7
Number of
Stop bits
00:
01:
10:
11:
invalid
1 bit
1.5 bits
2 bits
Mode register
Baud Rate
Parity enable
0: disable
1: enable
Character length
Parity
0: odd
1: even
00:
01:
10:
11:
5 bits
6 bits
7 bits
8 bits
68
70
71
Programming 8251
Baud Rate factor
Ratio between the clock applied to TxC-RxC inputs and the desired
baud rate
For example
To use transmitter clock (TXC) of 19,200Hz
for transmitting data at 1200 Bd
The baud rate factor = 19,200/1200 or 16x
In synchronous data transfer,
D1- D0 = 00
Baud rate will be same as the TxC and RxC
72
TxE:
DTR:
RxE:
IR
RTS
ER
SBRK
RxE
DTR
TxE
Command register
73
74
Programming 8251
8251 status register
DSR
SYNDET
FE
OE
PE
status register
75
Asynchronous Transmission
Figure below shows the polarities used on EIA-232 circuits
While there are no data to send (idle), the data circuit is at a
negative voltage
76
77
78
79
Write
start
start
Check RxRDY
Check TxRDY
Is it logic 1?
No
Is it logic 1?
Yes
Read data register*
end
* This clears RxRDY
No
Yes
Write data register*
end
* This clears TxRDY
80
Programming 8251
Q1. Write an 8086 assembly language procedure to transmit the contents of
register AH to the 8251 USART and out through its serial data pin, when the
TxRDY bit (bit 0 in the Control register) is set. Assume a Data and Control
address of FEH and FFH, respectively.
CONTROL
EQU FFH
DATA
EQU FEH
SEND PROC NEAR
PUSH AX
SEND1:
IN AL, CONTROL ; Is TxRDY? = 1
TEST AL, 01H ; 0000 0001
JZ SEND1
; Transmit data
MOV AL, AH
OUT DATA, AL ; Transmit a Character
POP AX
RET
SEND ENDP
81
Programming 8251
Q2. Write an 8086 assembly language procedure to test the RxRDY bit
(bit 1 in the Control register), to decide if the 8251 has received data, and
then return with the received data in register AL. Assume a Data and
Control address of C2H and C3H, respectively.
CONTROL
EQU C3H
DATA
EQU C2H
RECV PROC NEAR
PUSH AX
RECV1:
IN AL, CONTROL ; Is RxRDY? = 1
TEST AL, 02H ; 0000 0010
JZ RECV1
; Read Data
IN AL, DATA ; Receive a character
POP AX
RET
82
Errors
Parity error: Received data has wrong parity
error -- transmission bit flip due to noise.
83
External Interface
Parallel printer interface
A simple parallel interface
Uses 25-pin DB-25
8 data signals
Latched by strobe (pin 1)
85
DMA
86