Kadam
Department of Computer
Science, Yogeshwari
Electronic
Devices
Desired
Behavior
computer
organization
Electronic
Devices
software
General
Purpose
Computer
Desired
Behavior
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Machine Organization
How the hardware implements ISA ?
Physical View
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To PowerPC architecture
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om
Technology
Programming
Languages
Applications
Computer
Architecture
Operating
Systems
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History
software
instruction set
hardware
Designing Computers
All computers more or less based on
the same basic design, the Von
Neumann Architecture!
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Memory
ALU (Arithmetic/Logic Unit)
Control Unit
Input / Output System (I/O)
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Memory
Control Unit
ALU
Store data and program
Execute program
Do arithmetic/logic operations
requested by program
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Communicate with
"outside world", e.g.
Screen
Keyboard
Storage devices
...
Simplified Architecture
Source: Wikipedia
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Memory Subsystem
Memory, also called RAM (Random
Access Memory),
Consists of many memory cells (storage units)
of a fixed size.
Each cell has an address associated with it: 0, 1,
RAM
Need to distinguish
between
the address of a memory
cell and the content of a
memory cell
N
0000000000000001
0
1
2
2N
...
1 bit
2N-1
14
Memory sizes:
Kilobyte
(KB) = 210 =
bytes ~ 1 thousand
Megabyte(MB)
= 220 =
bytes ~ 1 million
Gigabyte
(GB) = 230 =
bytes ~ 1 billion
1,024
1,048,576
1,073,741,824
Operations on Memory
Fetch (address):
Fetch a copy of the content of memory cell with the
specified address.
Non-destructive, copies value in memory cell.
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Store(address, value)
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Sequential Access
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Storage Devices
I/O Controllers
Speed of I/O devices is slow
compared to RAM
RAM
~ 50 nsec.
Hard-Drive ~ 10msec. = (10,000,000
nsec)
Solution:
I/O Controller, a special purpose
processor:
Has a small memory buffer, and a control
logic to control I/O device (e.g. move disk
arm).
Sends an interrupt signal to CPU when done
read/write.
Data transferred
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ALU circuitry:
Contains an array of circuits
to do mathematical/logic
operations.
Bus:
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Data path interconnecting
.com
Machine Language
Instructions
Example: ADD X, Y
(Add content of
memory
X and
Y, and store
Opcode (8locations
bits)
Address
1 (16 bits)
Address back
2 (16 bits)in
memory location Y).
00001001
0000000001100011
0000000001100100
Assume: opcode for ADD is 9, and addresses
X=99, Y=100
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STORE X
X to R
location X
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MOVE
Compare
COMPARE X, Y
Control
HALT
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Example
Pseudo-code: Set A to B + C
Assuming variable:
A stored in memory cell 100, B stored
in memory cell 150, C stored in
memory cell 151
Machine language (really in binary)
LOAD
150
ADD 151
STORE 100
or
(ADD 150, 151, 100)
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IR
Instruction
Decoder
von Neumann
Architecture
Fetch instruction
Decode instruction
Execute instruction
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End of loop
Decode Phase
IR -> Instruction decoder (decode
instruction in IR)
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Instruction decoder will then generate the
Example:
LOAD X (load value in addr. X into
register)
IR_address -> MAR
Fetch signal
MDR --> R
ADD X
left as an exercise
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Operation
Meaning
0000
0001
0010
0011
0100
0101
0101
0111
LOAD X
STORE X
CLEAR X
ADD X
INCREMENT X
SUBTRACT X
DECREMENT X
COMPARE X
CON(X) --> R
R --> CON(X)
0 --> CON(X)
R + CON(X) --> R
CON(X) + 1 --> CON(X)
R - CON(X) --> R
CON(X) - 1 --> CON(X)
If CON(X) > R then GT = 1 else 0
If CON(X) = R then EQ = 1 else 0
If CON(X) < R then LT = 1 else 0
1000
1001
JUMP X
JUMPGT X
...
1101
1110
JUMPxx X
IN X
OUT X
1111
HALT
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Data Bus
Control Bus
I/O Device
Subsystem
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Memory
Subsystem
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Bus
Processor
Memory
Control
Cache
Datapath
Registers
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Devices
Input
Output
Instruction execution
cycle: fetch, decode,
execute.
Fetch: fetch next
instruction (using PC)
from memory into IR.
Decode: decode the
instruction.
Execute: execute
instruction.
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
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Internal
processor bus
Control signals
...
PC
Address line
Instruction
decoder and
control logic
MAR
MDR
Data line
IR
Y
Constant 4
MUX
RO
Select
ALU
control
lines
Add
Sub
:
:
R(n1)
ALU
Carry-in
XOR
TEMP
Z
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CLK
Bus
Bus
Read
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Address
Data
Read
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Address
Data
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Processor
logic capacity: about 30% per year
clock rate:
about 20% per year
Memory
DRAM capacity: about 60% per year (4x every 3
years)
Memory speed: about 10% per year
Cost per bit: improves about 25% per year
Disk
capacity: about 60% per year
Total use of data: 100% per 9 months!
Network Bandwidth
Bandwidth increasing more than 100% per year!
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DRAM
Size
64 Kb
256 Kb
1 Mb
4 Mb
16 Mb
64 Mb
256 Mb
1 Gb
In ~1985 the single-chip processor (32-bit) and the singleboard computer emerged
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