Each memory cell can hold one bit of information.

Memory cells are organized in the form of an array.

One row is one memory word.
All cells of a row are connected to a common line, known as the word
line.
Word line is connected to the address decoder.
Sense/write circuits are connected to the data input/output lines of the
memory chip.
Read operation : Address given to AoA1A2A3, R/W =1, sense circuit
Write operation : Address given to AoA1A2A3, data in write circuit,
R/W =0

FF
A0

A2

W1
Address
decoder

FF

A1

W0

Memory
cells

Sense/Write
circuit

Sense/Write
circuit

R/W

b1

b0

A3

W15

Sense/Write
circuit

Datainput /outputlines:

b7

16 x 8 organization

CS

128x 8 organization requires 19 external connection

1K x 1 organization requires 15 external connection

Two types
Static

RAM (SRAM)

Dynamic

RAM (DRAM)

Asynchronous DRAM (ADRAM)

Synchronous DRAM(SDRAM)

Double Data Rate SDRAM

 Static

RAMs (SRAMs):

Consist of circuits that are capable of retaining their state as

long as the power is applied.

Volatile memories, because their contents are lost when
power is interrupted.
Access times of static RAMs are in the range of few
nanoseconds.
However, the cost is usually high.

Two transistor inverters are cross connected to implement a

basic flip-flop.
The cell is connected to one word line and two bits lines by
transistors T1 and T2
When word line is at ground level, the transistors are turned off
and the latch retains its state
b

T1

T2

Wordline
Bitlines

 Read

operation:

word line is activated to close switches T1 and T2.

Sense/Write circuits at the bottom monitor the state

of b and b
Write

operation :

The state of the cell is placing on bit line b and its

complement on b,
activating the wordline.

Transistor (T3,T5 & T4,T6) pairs form the latch.

In state 1, the voltage at point X is maintained high

by having transistors T3 and T6 on.

Power supply, supply is 5V/3.3V.

If power is interrupted, the cells contents will be

lost.

Hence SRAMs are volatile.

Advantage
Low power consumption.
Very less access time in terms of
nanoseconds.

Do not retain their state indefinitely

Reasonable cost when compared to SRAMs.
Information is stored in the form of a charge on a
capacitor. This charge can be maintained for only
ten's of milliseconds.
Hence the contents are to be periodically refreshed
(i.e. restoring the capacitor to its full value) to store
the value for a longer time.
Contents may be refreshed while accessing them for
reading.

Two types of DRAMs

Asynchronous DRAM
Synchronous DRAM

Write Operation
T is turned on, and an appropriate voltage is applied to the
bit line. This causes the capacitor to posses some charge.
After the transistor is turned off, the capacitor begins to
discharge (due to capacitors leakage resistance)
Hence the information stored in the cell can be retrieved
correctly, only if it is read before the capacitors charge
drops below some threshold value.

Read Operation
The transistor is turned on.
A Sense Amplifier connected to the bit line detects whether
the charge on the capacitor is above threshold value.
If so, the bit line is driven to full voltage to represents the
logic value 1.
If the charge detected by sense Amplifier is below
threshold, the bit line is pulled to ground level representing
no charge.
Reading automatically refreshes the cell.

Each row can store 512 bytes.

12 bits to select a row, and 9
bits to select a group in a row.
Total of 21 bits.
First apply the row address,
RAS signal latches the row
address. Then apply the column
address, CAS signal latches the
address.
Timing of the memory unit is
controlled by a specialized unit
which generates RAS and
CAS.
This is asynchronous DRAM

RAS

Row
address
latch

A20 9 A8 0

Row
decoder

4096 5128
cellarray

Sense/
circuits
Write

Column
address
latch
CAS

Column
decoder

D7

D0

CS
R/W

Suppose if we want to access the consecutive

bytes in the selected row.
This can be done without having to reselect
the row.
Add a latch at the output of the sense circuits in each row.
All the latches are loaded when the row is selected.
Different column addresses can be applied to select and place

different bytes on the data lines.

Consecutive sequence of column addresses

can be applied under the control signal CAS,
without reselecting the row.
Allows a block of data to be transferred at a much faster rate than

random accesses.
A small collection/group of bytes is usually referred to as a block.

This transfer capability is referred to as the

fast page mode feature.

Operation

Refresh
counter

Row
address
latch

Row
decoder

Cellarray

Column
address
counter

Column
decoder

Read/Write
circuits&latches

Row/Column
address

Clock
R AS
CAS
R/ W

Moderegister
and
timingcontrol

Datainput
register

Dataoutput
register

CS

Data

is directly synchronized
with processor clock signal.
The outputs of the sense circuits a
connected to a latch.
During a Read operation, the
contents of the cells in a row are
loaded onto the latches.
During a refresh operation, the
contents of the cells are refreshed
without changing the contents of
the latches.
Data held in the latches correspon
to the selected columns are transfe
to the output.
For a burst mode of operation,
successive columns are selected us
column address counter and clock.
CAS signal need not be generated
externally. A new data is placed du
raising edge of the clock

 Memory

latency is the time it takes to

transfer a word of data to or from
memory
Memory bandwidth is the number of
bits or bytes that can be transferred in
one second.
DDRSDRAMs
Cell array is organized in two banks

A0
A1

21bit
addresses

19bitinternalchipaddress

A19
A20

2bit
decoder

512K 8
memorychip

D3124

D2316

D 158

512K 8memorychip

19bit
address

8bitdata
input/output

Chipselect

D70

Implement a memory unit of 2M

words of 32 bits each.
Use 512x8 static memory chips.
Each column consists of 4 chips.
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
select the row, by activating the
four Chip Select signals.
19 bits are used to access specific
byte locations inside the selected
chip.

Large dynamic memory systems can be

implemented using DRAM chips in a similar way
to static memory systems.
Placing large memory systems directly on the
motherboard will occupy a large amount of
space.

Also, this arrangement is inflexible since the memory system cannot be expanded
easily.

Packaging considerations have led to the

development of larger memory units known as
SIMMs (Single In-line Memory Modules) and
DIMMs (Dual In-line Memory Modules).
Memory modules are an assembly of memory
chips on a small board that plugs vertically onto
a single socket on the motherboard.

Occupy less space on the motherboard.

Allows for easy expansion by replacement .

Recall that in a dynamic memory chip, to reduce

the number of pins, multiplexed addresses are
used.
Address is divided into two parts:

High-order address bits select a row in the array.

They are provided first, and latched using RAS signal.
Low-order address bits select a column in the row.
They are provided later, and latched using CAS signal.

However, a processor issues all address bits at

the same time.
In order to achieve the multiplexing, memory
controller circuit is inserted between the
processor
and memory.

Row/Column
address

Address

RAS

R/ W
Processor

Request

Memory
controller

R/ W
CS

Clock

Clock

Data

24

CAS
Memory