CMOS Arithmetic Circuits

KTH/ESDlab/HT

04/25/16

Multiplication of numbers

KTH/ESDlab/HT

04/25/16

Datapath circuit techniques

for adders

KTH/ESDlab/HT

04/25/16

Binary adder

KTH/ESDlab/HT

04/25/16

Binary adder

KTH/ESDlab/HT

04/25/16

Special trick for reducing No of transistor

Cout = AB + CIN.(A + B)

SUM = ABCCN + COUT (A + B + CIN)

The advantage of these type realization is that transistor count is less as

compared to earlier realization using expression of slide 5.

KTH/ESDlab/HT

04/25/16

CMOS full adder

KTH/ESDlab/HT

04/25/16

Mirror Adders

KTH/ESDlab/HT

As discussed is class, Mirror adder circuit is having symmetrical N block and

P block.

04/25/16

Ripple carry adder

KTH/ESDlab/HT

04/25/16

Pipelined adder

KTH/ESDlab/HT

04/25/16

10

Carry bypass adder

KTH/ESDlab/HT

04/25/16

11

Carry bypass adder

KTH/ESDlab/HT

04/25/16

12

Linear carry select adder

KTH/ESDlab/HT

04/25/16

13

Linear carry select adder: critical path

KTH/ESDlab/HT

04/25/16

14

Carry look-ahead adder

KTH/ESDlab/HT

04/25/16

15

Carry look-ahead circuit structures

KTH/ESDlab/HT

04/25/16

16

Carry save (CSA) and carry propagate (CPA) adders

KTH/ESDlab/HT

04/25/16

17

Adder delays

KTH/ESDlab/HT

04/25/16

18

Adder delays summary

KTH/ESDlab/HT

04/25/16

19

Datapath circuit techniques

for multipliers

KTH/ESDlab/HT

04/25/16

20

Multiplier definition

KTH/ESDlab/HT

04/25/16

21

Binary multiplication

KTH/ESDlab/HT

04/25/16

22

Indirect multiplication

KTH/ESDlab/HT

04/25/16

23

Array multiplier

KTH/ESDlab/HT

04/25/16

24

MxN array multiplier critical path

KTH/ESDlab/HT

04/25/16

25

Carry ripple vs. carry save array multiplier

KTH/ESDlab/HT

04/25/16

26

Carry save multiplier

KTH/ESDlab/HT

04/25/16

27

Adder cells in array multiplier

KTH/ESDlab/HT

04/25/16

28

Array multiplier floorplan

KTH/ESDlab/HT

04/25/16

29

Wallace tree multiplier

KTH/ESDlab/HT

04/25/16

30

Wallace tree multiplier

KTH/ESDlab/HT

04/25/16

31

Wallace tree multiplier

KTH/ESDlab/HT

04/25/16

32

Dadda tree multiplier

KTH/ESDlab/HT

04/25/16

33

Serial-serial multiplier

KTH/ESDlab/HT

04/25/16

34

Serial-parallel multiplier

KTH/ESDlab/HT

04/25/16

35

Parallel vs. serial multipliers

KTH/ESDlab/HT

04/25/16

36

Parallel vs. serial multipliers

KTH/ESDlab/HT

04/25/16

37

Multiplier performance

KTH/ESDlab/HT

04/25/16

38

Multiplier performance

KTH/ESDlab/HT

04/25/16

39

Multiplier summary

KTH/ESDlab/HT

04/25/16

40

Other datapath elements

KTH/ESDlab/HT

04/25/16

41

Binary shifter

KTH/ESDlab/HT

04/25/16

42

Barrel shifter

KTH/ESDlab/HT

04/25/16

43

4x4 barrel shifter

KTH/ESDlab/HT

04/25/16

44

Logarithmic shifter

KTH/ESDlab/HT

04/25/16

45

Power considerations in datapath structures

KTH/ESDlab/HT

04/25/16

46

Reducing supply voltage

KTH/ESDlab/HT

04/25/16

47

Reducing supply voltage

KTH/ESDlab/HT

04/25/16

48

Architecture trade-offs: reference datapath

KTH/ESDlab/HT

04/25/16

49

Parallel datapath

KTH/ESDlab/HT

04/25/16

50

Pipelined datapath

KTH/ESDlab/HT

04/25/16

51

Datapath architecture summary

KTH/ESDlab/HT

04/25/16

52

Glitching in NOR chain

KTH/ESDlab/HT

04/25/16

53

Glitching in RCA

KTH/ESDlab/HT

04/25/16

54

Switching activity in adders

KTH/ESDlab/HT

04/25/16

55

Switching activity in multipliers

KTH/ESDlab/HT

04/25/16

56

Layout strategy for datapath

KTH/ESDlab/HT

04/25/16

57

Layout strategy for datapaths

KTH/ESDlab/HT

04/25/16

58

Cell area: 2 vs. 3 metal layer process

KTH/ESDlab/HT

04/25/16

59

Summary

KTH/ESDlab/HT

04/25/16

60