Lesson 4

Synchronous Design Architectures:

Control Unit Design
(part three)

Sept. 2005

EE37E Adv. Digital

Electronics

Topics

Introduction
Hardwired vs. Microprogrammed Control
Hardwired Control
Microprogrammed Control
High-level Synthesis of Control Units

Sept. 2005

EE37E Adv. Digital

Electronics

1. Introduction
The control subsystem is a (synchronous)
sequential machine. That has the following
characteristics:
INPUTS: control inputs to the system and conditions
from the data subsystem
OUTPUTS: control signals
ONE STATE PER STATEMENT IN REGISTERTRANSFER SEQUENCE
TRANSITION FUNCTION CORRESPONDS TO
SEQUENCING
OUTPUT FOR EACH STATE CORRESPONDS
TOCONTROL SIGNALS
Sept. 2005

EE37E Adv. Digital

Electronics

2. Hardwired vs. microcoded control

Hardwired control has a state register and
random logic.
A microcoded (microprogrammed) machine has
a state register which points into a microcode
memory.
Styles are equivalent; choice depends on
implementation considerations.

Sept. 2005

EE37E Adv. Digital

Electronics

3. Hardwired Control
Two types of sequencing:
UNCONDITIONAL: only one successor to a state
CONDITIONAL: several possible successors
depending on the value of a condition

Because unconditional case is much more

frequent in most execution graphs, a favored
implementation of the sequencer consists of
using a counter in which consecutive states in
the sequence are assigned to the counter.

Sept. 2005

EE37E Adv. Digital

Electronics

 If the number of states is small, structures with

one flip-flop per state result is straightforward
mapping between the sequence (state diagram)
and implementation is recommended.
These also have the advantage that no decoder
is required for the generation of the control
signals.

Sept. 2005

EE37E Adv. Digital

Electronics

 Let us discuss the correspondence among the

state diagram and the one flip-flop per state
implementation:
The simplest case is the state with one predecessor,
as shown in Figure 4.3.1a, the corresponding
implementation is in Figure 4.3.1a.
A more general case is depicted in Figures 4.3.1b and
4.3.1b

Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.1: PRIMITIVES FOR THE one ip-op per state"

APPROACH.
Sept. 2005
EE37E Adv. Digital
Electronics

Control signals
They depend on the state, conditions, and the external
inputs to the system.
The conditional control signals can be implemented in
two ways, corresponding to the Mealy and Moore
models of sequential systems.
Consider the following statement:
IF (sign = 0) then A <= B;
Else
C<=D;
End If;
Let C_1 and C_2 the control signals for loading A and C,
respectively.
Figure 4.3.2. Illustrates the two alternatives.
Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.2: IMPLEMENTATION ALTERNATIVES FOR CONTROL

SIGNALS: a) Moore-type implementation; b) Mealy-type
implementation.
Often a control signal is active during several consecutive states. Instead
of generating such a signal in each relevant state, its possible to
introduce a clocked cell that can be set when the signal becomes active
and cleared when it become inactive, as illustrated in figure 4.3.3.

Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.3: CLOCKED CELL: a) STATE DIAGRAM; b) IMPLEMENTATION OF

SIGNALS c 1 and c 3; c) TIMING DIAGRAM.

Sept. 2005

EE37E Adv. Digital

Electronics

Design Example
Let us now illustrate the use of some of the components
discussed previously.

A VHDL specification is given in Figure 4.3.4.

For an implementation we need to developed a structural
description having as components the data and control
subsystems.
Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.4: Block diagram and entity declaration

Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.5: Architecture specification

Sept. 2005
EE37E Adv. Digital
Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.6: DATA SUBSYSTEM FOR DESIGN EXAMPLE

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Figure 4.3.6: IMPLEMENTATION OF CONTROL SUBSYSTEM.

Sept. 2005

EE37E Adv. Digital

Electronics