Cse477 23 Memories

CSE477
VLSI Digital Circuits

Fall 2002
Lecture 23: Semiconductor
Memories
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

CSE477 L23 Memories.1
Irwin&Vijay, PSU, 2002
Review: Basic Building Blocks
Datapath
Execution units
- Adder, multiplier, divider, shifter, etc.
Register file and pipeline registers
Multiplexers, decoders
Control
Interconnect
Finite state machines (PLA, ROM, random logic)
Switches, arbiters, buses
Memory
Caches (SRAMs), TLBs, DRAMs, buffers
A Typical Memory Hierarchy
By taking advantage of the principle of locality:
Present the user with as much memory as is available in the

cheapest technology.
Provide access at the speed offered by the fastest technology.

On-Chip Components
Control
eDRAM
.1s
1s
10s
100s
1,000s
Size (bytes):
100s
Ks
10Ks
Ms
Ts
Cost:
ITLB DTLB
Speed (ns):
Datapath
RegFile
Instr Data
Cache Cache
Secondary
Memory
(Disk)
Second
Level
Cache
(SRAM)
highest
Main
Memory
(DRAM)
lowest
Semiconductor Memories
RWM
NVRWM
ROM
Maskprogrammed
Random
Access
Non-Random
Access
EPROM
SRAM
(cache,
register file)
FIFO/LIFO
E2PROM
DRAM
Shift Register
FLASH
Electricallyprogrammed
(PROM)
CAM
Growth in DRAM Chip Capacity

1000000
256,000
Kbit capacity
100000
64,000
16,000
10000
4,000
1000
1,000
256
100
64
10
1980
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
Year of introduction
1D Memory Architecture
m bits
S0
Word 0
S0
Word 0
S1
Word 1
S1
Word 1
S2
Word 2
A0
S2
Word 2
A1
S3
S3
Storage
Cell
Ak-1
Sn-2
Word n-2
Sn-1
Word n-1
Input/Output
n words n select signals

Decoder
n words
m bits
Sn-2
Sn-1
Storage
Cell
Word n-2
Word n-1
Input/Output
Decoder reduces # of inputs

k = log2 n
bit line
2k-j
Ak-1
Row Decoder
Aj
Aj+1
Column
Address
Row Address
word line
A0
A1
Aj-1
storage
(RAM) cell
m2j
Column Decoder
Sense Amplifiers
selects appropriate
word from memory row
amplifies bit line swing
Read/Write Circuits
Input/Output (m bits)
Block Column
Addr
Addr
Row
Addr
Input/Output (m bits)
Advantages:
1. Shorter word and/or bit lines
2. Block addr activates only 1 block saving power
Read Only Memories (ROMs)
Precharged MOS NOR ROM

Vdd
0 1 precharge
WL(0)
GND
0 1 WL(1)
WL(2)
GND
WL(3)
BL(0)
1
0
BL(1)
1
1
BL(2)
1
1
BL(3)
1
0
MOS NOR ROM Layout

Metal1 on top of diffusion
WL(0)
GND (diffusion)
WL(1)
Basic cell
10 x 7
Metal1
Polysilico
n
GND (diffusion)
WL(2)
WL(3)
BL(0) BL(1) BL(2) BL(3)
Only 1 layer (contact mask) is used to program memory array, so

programming of the ROM can be delayed to one of the last process steps.
Transient Model for NOR ROM

precharge
poly
metal1
rword
BL
Cbit
WL
cword
Word line parasitics

Resistance/cell: 35
Wire capacitance/cell: 0.65 fF
Gate capacitance/cell: 5.10 fF
Bit line parasitics
Resistance/cell: 0.15
Wire capacitance/cell: 0.83 fF
Drain capacitance/cell: 2.60 fF
Propagation Delay of NOR ROM
Word line delay
Delay of a distributed rc-line containing M cells

tword = 0.38(rword x cword) M2
= 20 nsec for M = 512
Bit line delay
Assuming min size pull-down and 3*min size pull-up with

reduced swing bit lines (5V to 2.5V)
Cbit = 1.7 pF and IavHL = 0.36 mA so
tHL = tLH = 5.9 nsec
Read-Write Memories (RAMs)
Static SRAM
data is stored as long as supply is applied
large cells (6 fets/cell) so fewer bits/chip
fast so used where speed is important (e.g., caches)
differential outputs (output BL and !BL)
use sense amps for performance
compatible with CMOS technology
Dynamic DRAM
periodic refresh required
small cells (1 to 3 fets/cell) so more bits/chip
slower so used for main memories
single ended output (output BL only)
need sense amps for correct operation
not typically compatible with CMOS technology
Memory Timing Definitions

Read Cycle
Read
Read Access
Write
Read Access
Write
Setup
Write Cycle
Write
Hold
Data
Data Valid
4x4 SRAM Memory

read
precharge
enable
A1
A2
clocking and
control
Row Decoder
2 bit words
A0
bit line precharge

WL[0]
!BL BL
WL[1]
WL[2]
WL[3]
Column Decoder
sense amplifiers
BL[i] BL[I+1]
write circuitry
Sense Amps
Row Decoder
2D Memory Configuration
Sense Amps
Decreasing Word Line Delay
Drive the word line from both sides

driver
WL
polysilicon word line
driver
metal word line
Use a metal bypass

WL
polysilicon word line
metal bypass
Use silicides
Decreasing Bit Line Delay (and Energy)
Reduce the bit line voltage swing
need sense amp for each column to sense/restore signal
Isolate memory cells from the bit lines after sensing (to
prevent the cells from changing the bit line voltage
further) - pulsed word line
generation of word line pulses very critical

- too short - sense amp operation may fail
- too long - power efficiency degraded (because bit line swing size depends
on duration of the word line pulse)
use feedback signal from bit lines
Isolate sense amps from bit lines after sensing (to

prevent bit lines from having large voltage swings) - bit
line isolation
Pulsed Word Line Feedback Signal

Read
Word line
Dummy
bit lines
Bit lines
Complete
10%
populated
Dummy column
height set to 10% of a regular column and its cells are tied to
a fixed value
capacitance is only 10% of a regular column
Pulsed Word Line Timing
Read
Complete
Word line
Bit line
Dummy bit line
V = 0.1Vdd
V = Vdd
Dummy bit lines have reached full swing and trigger

pulse shut off when regular bit lines reach 10% swing
Bit Line Isolation

bit lines
V = 0.1Vdd
isolate
Read
sense
amplifier
sense
V = Vdd
sense amplifier outputs
6-transistor SRAM Cell

WL
M2
M5
M6
!Q
M1
!BL
M4
Q
M3
BL
Next Lecture and Reminders
Next lecture
SRAM, DRAM, and CAM cores

- Reading assignment Rabaey, et al, 12.2.2-12.2.3
Reminders
Project final reports due December 5th
Final grading negotiations/correction (except for the final

exam) must be concluded by December 10th
Final exam scheduled

- Monday, December 16th from 10:10 to noon in 118 and 121
Thomas

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CSE477

VLSI Digital Circuits

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

Irwin&Vijay, PSU, 2002

Review: Basic Building Blocks

Register file and pipeline registers

Finite state machines (PLA, ROM, random logic)

Switches, arbiters, buses

Caches (SRAMs), TLBs, DRAMs, buffers

CSE477 L23 Memories.2

Irwin&Vijay, PSU, 2002

A Typical Memory Hierarchy

By taking advantage of the principle of locality:

Present the user with as much memory as is available in the

Provide access at the speed offered by the fastest technology.

CSE477 L23 Memories.4

Irwin&Vijay, PSU, 2002

Growth in DRAM Chip Capacity

Irwin&Vijay, PSU, 2002

n words n select signals

Decoder reduces # of inputs

Irwin&Vijay, PSU, 2002

Irwin&Vijay, PSU, 2002

Read Only Memories (ROMs)

CSE477 L23 Memories.9

Irwin&Vijay, PSU, 2002

Precharged MOS NOR ROM

MOS NOR ROM Layout

BL(0) BL(1) BL(2) BL(3)

Only 1 layer (contact mask) is used to program memory array, so

Irwin&Vijay, PSU, 2002

Transient Model for NOR ROM

Word line parasitics

Irwin&Vijay, PSU, 2002

Propagation Delay of NOR ROM

Word line delay

Delay of a distributed rc-line containing M cells

Bit line delay

Assuming min size pull-down and 3*min size pull-up with

CSE477 L23 Memories.14

Irwin&Vijay, PSU, 2002

Read-Write Memories (RAMs)

data is stored as long as supply is applied

large cells (6 fets/cell) so fewer bits/chip

fast so used where speed is important (e.g., caches)

differential outputs (output BL and !BL)

use sense amps for performance

compatible with CMOS technology

periodic refresh required

small cells (1 to 3 fets/cell) so more bits/chip

slower so used for main memories

single ended output (output BL only)

need sense amps for correct operation

not typically compatible with CMOS technology

CSE477 L23 Memories.15

Irwin&Vijay, PSU, 2002

Memory Timing Definitions

CSE477 L23 Memories.16

Irwin&Vijay, PSU, 2002

4x4 SRAM Memory

bit line precharge

CSE477 L23 Memories.17

Irwin&Vijay, PSU, 2002

CSE477 L23 Memories.18