Unit 2 & 3 (1 chapter)

Unit Chapters
2

Ch 3: 8085 Instruction Set

Addressing Modes
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branching Instructions
Stack and Subroutine
Writing Assembly Language
Programs

Counters and Time Delays,

Stack
Counter and Time delay
Different Methods of
generating Time delay
Programs
Stack , Subroutine
Restart Conditional call and
Return Instructions
Advanced Subroutine Concepts
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Memory and I/O interfacing

Memory interfacing
Decoding Methods
Basic Interfacing Concepts
Interfacing Output Devices
Interfacing Input Devices
Memory Mapped I/O and
Peripheral Mapped I/O

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Memory structure & its requirements

Data Lines

ROM

RAM
Input Buffer

Address
Lines

WR

CS

Output Buffer

Address
Lines

RD

CS

Output Buffer

RD

Data Lines
Date
Lines

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Interfacing Memory
Accessing memory can be summarized into
the following three steps:
Select the chip.
Identify the memory location.
Enable the appropriate read or write buffer.
Translating this to microprocessor domain:
The microprocessor places a 16-bit address on the
address bus.
Part

of the address bus will select the chip and the other
part will go through the address decoder to select the
register.

The

signals IO/M and RD combined indicate that a

memory read operation
is in progress. The MEMR2014
signal
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The Overall Structure

A15- A10

Chip Selection
Circuit

8085
CS

A15-A8
ALE

A9- A0
AD7-AD0

WR

RD

IO/M

Latch

A7 - A 0

1K Byte
Memory
Chip

D7- D0
RD

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WR

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Decoding the address lines

Figure shows two techniques to decode
address lines:
Using the NAND gates.
Using the 3-to-8 decoder.

The output of NAND gate can be activated

when all the input A12-A15 is at logic 1.

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Decoding the address lines

Using the 3-to-8 (74LS138) decoder:
Combining the input A12-A14 to obtain
output at O7 when A12= A13= A14=1.
The enable pins E1 and E2 are enabled by
grounding them and the A15 signal should
be at logic 1 to enable the E3.

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Memory Interfacing

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Address Decoding
The logic combination at address A15-A12
must have logic 0000 to activate the Chip
Enable,
and the address A11-A0 can have all logic
combinations either 0 or 1.
Therefore the range of address for this chip
A is
A 0000H
A A
A A0FFFH;
A A A A A A A A A A
until
15

14

0 0
0
0 0
0 0

13

12

Chip Enable
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11

10

0 0 0
01 01 01
1 1 1

0
1

0
1

0 0
1 1

0
1

0
1

Register Select
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Address Decoding 2K RAM

Address Range?
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Decoding Techniques
Absolute Decoding:
In absolute decoding address lines which are
not connected to the memory chip are used
to generate the Chip Enable (CE) signal.

Partial Decoding
In Partial Decoding all remaining address
lines which are not connected to the memory
chip may not be used to generate the Chip
Enable (CE) signal.

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Address Decoding (Absolute)

Note: A11 is not used for
RAM.

RAM

RO
M
RO
M

RAM

Address Range ?
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Examples

1. Design 8085 Microprocessor System

such that it should contain 4K bytes of
EPROM and 4K bytes of RAM. Starting
Address of EPROM Should be 0000H and
starting address of RAM should be
6000H.
2. Design 8085 Microprocessor System
such that it should contain 16K bytes of
EPROM using two 8K bytes of EPROMS
and 4K bytes of RAM using two 2K bytes
of RAM.
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Examples
Interface 2KB of RAM to 8085 Using (1K x 4)
chips , 74LS138(3 to 8 decoder) and full
address decoding.

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Comparison of decoding type

Absolute
Decoding

Partial Decoding

All Remaining Address Few Remaining Address

lines are decoded
lines are decoded
More
Hardware
required
Higher cost

is Less Hardware Required

Less Cost

No Multiple Addresses

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Multiple Addresses

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Interfacing I/O

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Interfacing I/O Devices

Using I/O devices data can be transferred
between the microprocessor and the
outside world.
This can be done in groups of 8 bits using
the entire data bus. This is called parallel
I/O.
The other method is serial I/O where one
bit is transferred at a time using the SID
and SOD pins on the Microprocessor.
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Basic Interfacing Concepts

An i/o device
can be interfaced with
Microprocessor using peripheral i/o
or
memory mapped i/o.
In the peripheral i/o, the instruction IN and
OUT are used to data transfer, and device is
identified using 8-bit address.
In the Memory Mapped i/o, memoryrelated
instructions are used for data transfer, and
the device is identified using a 16-bit address.
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Peripheral I/O instructions

The Instruction IN input data from input
device such as keyboard in to the
accumulator and the instruction OUT sends
the content of accumulator to an output
device such as LED.
These are 2 byte instructions, with second
byte specifying the address or the port
number of an i/o device.

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Peripheral I/O instructions

Op
code
OUT

Operan
Description
d
8-bit
This instruction transfers the data
Address from the accumulator to the output
device.

Op
code
IN

Operan
Description
d
8-bit
This instruction transfers the data
Address from
the
output
device
to
accumulator.

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Timing Diagram for OUT instruction

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Timing Diagram for IN instruction

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I/O Peripherals Interface

Note: In IO interfacing, only one segment of the address

bus (low or high addresses) is sufficient (both segment
have
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M&I address).
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Decoding Techniques
Absolute Decoding:
All address lines are used for generating
the device address.

Partial Decoding:
In partial decoding all the address lines are
not used for generating the device address.

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Partial Decoding

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Input Interface

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I/O interface using decoder

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I/O interface using decoder

Circuit in previous figure decode input and
output device at once using 3-to-8
decoder and four input NAND gates.
The address lines A2, A1 and A0 are used as
inputs to decoder, and the remaining line
address A7 to A3 is used to enable the
decoder chip.
The decoder has eight output; therefore
we can use the decoder to address eight
kind of input and output devices.
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Seven segment display output

interface.

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AV / M&I

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Seven segment display interface

7-segment display consists of a few LEDs
and are arranged physically as shown in
figure.
It has seven segment from A to G that
normally connected to data bus D0 to D6
respectively.
If decimal point is used, D7 will be connected
to DP; and left unconnected if it is unused.

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Seven segment display interface

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Seven segment display interface

Fig. shows the example to interface seven
segment display and address decoder with an
address of FDH.
Suppose to display number 4 at seven
segment display, therefore the segment F, G,
B and C have to be activated.
Follows are the instructions to execute it:
MVI A, 66H
Data lines: D
OUT FDH D D D D D D
7

D0
Bits: X
1
0
Segments NC G
:
A
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1
F

0
E

0
D

1
C

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1 = 66 H

B
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 Write ALP to display 0 to 9 on 7 segment.

(Continuously)

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Memory Mapped I/O

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 In memory mapped i/o the input and

output devices are assigned and identified
by 16 bit address.
To
transfer
data
between
the
Microprocessor and i/o devices , memory
related instructions(LDA, STA) and memory
control signals are used.

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AV / M&I

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Difference between Peripheral and Memory mapped I/O

Peripheral I/O (I/O mapped I/O)

Memory Mapped I/O

8 bit port Address

16 bit Port address

Maximum 256 I/O can be

interfaced

Maximum 65536 I/O ports can be

interfaced

Less address decoding hardware is More address decoding hardware is

required as only 8 address lines are required as 16 address lines are
decoded.
decoded.
IOR and IOW will be the control
signals

MEMR and MEMW will be the control

signals.

IN and OUT are only instruction to

access the I/O device.

Any memory related instruction can

be used, MOV , STA , LDA

I/O can communicate with

accumulator only.

I/O can communicate with any

registers.

I/O and memory can have same

address.

I/O and memory cant have the

same address.

Arithmetic and logical instructions

Arithmetic and Logical instructions
can not be performed directly on
can be performed directly on I/O.
the AV
data
at I/O
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Counters and Time

delay

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Counters
A loop counter is set up by loading a register
with a certain value
Then using the DCR (to decrement) and INR
(to increment) the contents of the register
are updated.
A loop is set up with a conditional jump
instruction that loops back or not depending
on whether the count has reached the
termination count.
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Counters
The operation of a loop counter can be
described using the following flowchart.
Initialize
Body of loop

Update the count

No

Is this
Final
Count?
Yes

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Delays
each instruction passes through different
combinations of Fetch, Memory Read, and
Memory Write cycles.
Knowing the combinations of cycles, one
can calculate how long such an instruction
would require to complete.

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Delays
Knowing how many T-States an instruction
requires, and keeping in mind that a T-State
is one clock cycle long, we can calculate the
time using the following formula:
Delay = No. of T-States / Frequency
For example a MVI instruction uses 7 TStates. Therefore, if the Microprocessor is
running at 2 MHz, the instruction would
require 3.5 Seconds to complete.
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Delay loops
We can use a loop to produce a certain
amount of time delay in a program.
The following is an example of a delay loop:
M VIC, FFH
7 T-States
LO O P D CR C 4 T-States
JN Z LO O P 10 T-States

The first instruction initializes the loop counter and is

executed only once requiring only 7 T-States.
The following two instructions form a loop that requires 14 TStates to execute and is repeated 255 times until C becomes
0.
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Delay Loops (Contd.)

We need to keep in mind though that in the last iteration of

the loop, the JNZ instruction will fail and require only 7 TStates rather than the 10.
Therefore, we must deduct 3 T-States from the total delay to
get an accurate delay calculation.
To calculate the delay, we use the following formula:
Tdelay = TO + TL
Tdelay = total delay
TO = delay outside the loop
TL = delay of the loop

TO is the sum of all delays outside the loop.

TL is calculated using the formula

TL = T X Loop T-States X N10
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Delay Loops (Contd.)

Using these formulas, we can calculate the
time delay for the previous example:
TO = 7 T-States
Delay of the MVI instruction

TL = (14 X 255) - 3 = 3567 T-States

14 T-States for the 2 instructions repeated 255 times
(FF16 = 25510) reduced by the 3 T-States for the final JNZ.

TDelay = (7 + 3567) X 0.5 Sec = 1.787 mSec

Assuming f = 2 MHz

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Using a Register Pair as a Loop Counter

Using a single register, one can repeat a loop for a maximum
count of 255 times
It is possible to increase this count by using a register pair for
the loop counter instead of the single register.

A minor problem arises in how to test for the final count

since DCX and INX do not modify the flags.

However, if the loop is looking for when the count

becomes zero, we can use a small trick by ORing the

two registers in the pair and then checking the zero flag.

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Using a Register Pair as a Loop Counter

The following is an example of a delay
loop set up with a register pair as the
loop counter.
LXIB, 1000H 10 T-States
LO O P D CX B 6 T-States
M O V A, C 4 T-States
O RA B 4 T-States
JN Z LO O P 10 T-States

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Using a Register Pair as a Loop Counter

Using the same formula from before, we can
calculate:
TO = 10 T-States

The delay for the LXI instruction

TL = (24 X 4096) - 3 = 98301 T- States

24 T-States for the 4 instructions in the loop repeated

4096 times (100016 = 409610) reduced by the 3 T-States
for the JNZ in the last iteration.

TDelay = (10 + 98301) X 0.5 mSec = 49.155 mSec

48
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Nested Loops
Nested loops can be
easily
setup
in
Assembly language by
using two registers for
the two loop counters
and updating the right
register in the right
loop.
In the figure, the
body of loop2 can
be before or after
loop1.

Initialize loop 2
Body of loop 2
Initialize loop 1
Body of loop 1
Update the count1

No

Is this
Final
Count?

Yes
Update the count 2

No

Is this
Final
Count?
Yes

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Nested Loops for Delay

Instead (or in conjunction with) Register
Pairs, a nested loop structure can be used to
increase the total delay produced.
M VIB, 10H
7 T-States
LO O P2: M VIC, FFH
7 T-States
LO O P1: D CR C 4 T-States
JN Z LO O P110 T-States
D CR B 4 T-States
JN Z LO O P210 T-States

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Delay Calculation of Nested Loops

The calculation remains the same except
that it the formula must be applied
recursively to each loop.
Start with the inner loop, then plug that delay
in the calculation of the outer loop.
Delay of inner loop
TO1 = 7 T-States
MVI C, FFH instruction

TL1 = (255 X 14) - 3 = 3567 T-States

14 T-States for the DCR C and JNZ instructions repeated 255
times (FF16 = 25510) minus 3 for the final JNZ.

TLOOP1 = 7 + 3567 = 3574 T-States

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Delay Calculation of Nested Loops

Delay of outer loop
TO2 = 7 T-States
MVI B, 10H instruction

TL1 = (16 X (21+ 3574)) - 3 = 57517 T-States

21 T-States for the MVI, DCR B and JNZ instructions and 3574
T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for
the final JNZ.

TDelay = 7 + 57517 = 57524 T-States

Total Delay
TDelay = 57524 X 0.5 Sec = 28.762 mSec

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 Write a Program to count 0 to F with a one second delay between

each count. At the count of F, the counter should reset itself to 0
to repeat the sequence continuously. Use register pair HL to set
up the delay, and display each count on display. Assume the clock
frequency = 1MHz

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Program
repeat:

MVI B,00H

7T

display:

OUT 80H

10T

LXI H , Count Value

10T

DCX H

6T

MOV A,L

4T

ORA H

4T

JNZ back

10T

INR B

4T

MOV A,B

4T

CPI 0FH

7T

JNZ display

10T

JZ repeat

10T

back:

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Counter design with time delay

Example :
Write a program to count number from FFH to 00H in a
system with time interval of 0.5 s.
Use C register as delay register with the delay of 1ms for
every count.
Display the count at the output port.

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MVI B, 00H
NEXT:

DCR B
MVI C, COUNT

DELAY: DCR C
JNZ DELAY
MOV A, B
OUT PORT
JMP NEXT

56
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57
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Example
Write a program to generate continuous
square wave with period of 500s. Assume
that system clock period is 325ns and use
bit D0 to output
the square wave.
500
s

After RLC

AND with 01H

Remaining
contents

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Program
ROTATE:

DELAY:

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MVI D,AAH
MOV A,D
RLC
MOV D,A
ANI 01H
OUT Port address
MVI B,COUNT
DCR B
JNZ DELAY
JMP ROTATE
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1. No of Instructions outside the loop:

1. Delay outside the loop: T0 = 46T States X 325ns =
14.95S
2. Loop Delay:
1. 14T states x 325ns x count
Total Delay
250s = 14.95s + 4.5s * Count
Count = 52.33
Hex 34H

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Stack and
Subroutine

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The Stack
The stack is an area of memory identified
by the programmer for temporary storage
of information.
The stack is a LIFO structure.
Last In First Out.

The stack normally grows backwards into

memory.
Memory
The Stack
grows
backwards
into memory

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The Stack
Given that the stack grows backwards into memory, it
is customary to place the bottom of the stack at the
end of memory to keep it as far away from user
programs as possible.
In the 8085, the stack is defined by setting the SP
(Stack Pointer) register.
LXISP, FFFFH

This sets the Stack Pointer to location FFFFH (end of

memory for the 8085).
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Saving Information on the Stack

Information is saved on the stack by PUSHing it on.

It is retrieved from the stack by POPing it off.

The 8085 provides two instructions: PUSH and POP
for storing information on the stack and retrieving it
back.

Both PUSH and POP work with register pairs

ONLY.

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The PUSH Instruction

PUSH B
Decrement SP
Copy the contents of register B to the
memory location pointed by SP
Decrement SP
Copy the contents of register C to the
memory location pointedFFFFby SP
FFFE

12

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F3

FFFD

SP

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The POP Instruction

POP D
Copy the contents of the memory
location pointed to by the SP register
E
Increment SP
Copy the contents of the memory
location pointed by the SP register D
Increment SP

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Operation of the Stack

During pushing, the stack operates in a

decrement then store style.
The stack pointer is decremented first, then
the information is placed on the stack.

During poping, the stack operates in a use

then increment style.
The information is retrieved from the top of
the
stack and then the pointer is
incremented.

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LIFO
The order of PUSHs and POPs must be opposite of
each other in order to retrieve information back into
its original location.
PU SH B
PU SH D
...
PO P D
PO P B

Reversing the order of the POP instructions will result

in the exchange of the contents of BC and DE.
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The PSW Register Pair

The 8085 recognizes one additional register pair called the
PSW (Program Status Word).

This register pair is made up of the Accumulator and

the Flags registers.

It is possible to push the PSW onto the stack, do whatever

operations are needed, then POP it off of the stack.

The result is that the contents of the Accumulator

and the status of the Flags are returned to what they
were before the operations were executed.
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Subroutines
A subroutine is a group of instructions that will be
used repeatedly in different locations of the program.
Rather than repeat the same instructions several

times, they can be grouped into a subroutine that is

called from the different locations.

In

Assembly

language,

subroutine

can

exist

anywhere in the code.

However,

it

is

customary

to

place

subroutines

separately from the main program.

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Subroutines

The 8085 has two instructions for dealing

with subroutines.
The CALL instruction is used to redirect
program execution to the subroutine.
The RET instruction is used to return the
execution to the main program.

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The CALL Instruction

CALL 4000H
Push

the

address

of

the

instruction

immediately following the CALL onto the

stack
Load the program counter with the 16-bit
address

supplied

with

the

CALL

2000CALL 4000
2003

instruction.

PC

2003
FFFB
FFFC
FFFD
FFFE
FFFF

PC

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03
20

SP

4000

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The RET Instruction

RET
Retrieve the return address from the
stack
Load the program counter with the return
address.
PC

2003
FFFB
FFFC
FFFD
FFFE
FFFF

4014. . .
4015RET

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03
20

SP

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Cautions

The RET instruction takes the contents of

the two memory locations from the stack
and uses these as the return address.
Do not modify the stack pointer in a
subroutine. You will loose the return
address.

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Passing Data to a Subroutine

In Assembly Language data is passed to a subroutine
through registers.
The data is stored in one of the registers by the calling

program and the subroutine uses the value from the

register.

The other possibility is to use agreed upon memory

locations.
The calling program stores the data in the memory location

and the subroutine retrieves the data from the location and
uses it.
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 If the subroutine performs operations on the contents

of the registers, then these modifications will be
transferred

back

to

the

calling

program

upon

returning from a subroutine.

If this is not desired, the subroutine should PUSH all

the registers it needs on the stack on entry and POP
them on return.
The original values are restored before execution
returns to the calling program.
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Cautions with PUSH and POP

There has to be as many POPs as there are
PUSHs.
If not, the RET statement will pick up the
wrong information from the top of the stack
and the program will fail.

It is not advisable to place PUSH or POP

inside a loop.
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Conditional CALL and RET Instructions

The 8085 supports conditional CALL and conditional
RET instructions.
The same conditions used with conditional JUMP

instructions can be used.

CC, call subroutine if Carry flag is set.
CNC, call subroutine if Carry flag is not set
RC, return from subroutine if Carry flag is set
RNC, return from subroutine if Carry flag is not set
Etc.
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Write a program to provide given on/off time to three

traffic lights (G,Y,R) and two pedestrian sign (Walk and
Dont walk). The signal lights and signs are turned on and
off by the data bits of an output port.

Lights

Data Bits

On time

1. Green

D0

15 seconds

2. Yellow

D2

5 seconds

3. Red

D4

20 seconds

4. Walk

D6

15 seconds

5. Dont walk

D7

25 seconds

The pedestrian should cross the road when the green light is on
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Time Sequence in
seconds

D
7

D6 D
5

D
4

D3 D
2

D
1

D
0

Hex
Cod
e

0 to 15 seconds

41H

15 to 20 Seconds

84H

20 to 40 Seconds

90H

80
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Program
LXI SP , 2000H
START:

MVI A, 41H
OUT PORT1
MVI B,15H
CALL DELAY
MVI A,84H
OUT PORT1
MVI B,05H
CALL DELAY
MVI A,90H
OUT PORT1
MVI B,14H

81
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CALL DELAY

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Program for delay subroutine

DELAY:

PUSH D
PUSH PSW

SECOND:

LXI D, COUNT

LOOP:

DCX D
MOV A,D
ORA E
JNZ LOOP
DCR B
JNZ SECOND
POP PSW
POP D
RET

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RST Instruction
RST instructions are 1 byte call instructions
that transfers the program execution to a
specific location. They are executes same as
call instruction. These instructions are
generally used in conjunction with interrupt
process.
RST
0

CALL 0000H

RST 4

CALL
0020H

RST
1

CALL 0008H

RST 5

CALL
0028H

RST
2

CALL 0010H

RST 6

CALL
0030H

RST
3

CALL 0018H

RST 7

CALL
0038H

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Advanced Subroutine Concepts

Nesting:
Subroutine calling another Subroutine
2090
H

CALL
2090H

Subroutine
1

203F
H

CALL
203FH
RET

AV / M&I

Subroutine
2

Indus University

RET

2014

Multiple Ending Subroutine

Subroutine

2050H
RZ
2058H
RC
2070H
RET
AV / M&I

Indus University

2014