Static Synchronous Series Compensator

Based on Voltage Source Converter with DSP TMS320LF2407A

Mahesh Kumar koli

M-Tech Power system
EEE Department

Project Guide
Dr. Sishaj P Simon
Electrical & Electronics Engg. Deptt.
National Institute of Technology Tiruchirappalli
Objective

• To design a DSP(TMS320LF2407) based

SSSC.
• Hardware implementation of the SSSC.
• Power flow control(Active and Reactive
power).
• For increasing the power capability and
controllability of the transmission lines.
•
Introduction

Ø The static synchronous series compensator (SSSC), using a

based on VSC-DSP to inject a controllable voltage in
quadrature with the line current of a power system, its
provide both capacitive and inductive impedance
compensation independent of the line current. The VSC
based series compensator, is called static synchronous
series compensator (SSSC).
Ø
•
•
•
Equivalent Circuit Diagram of SSSC

Vqlags by 90° plus (Capacitive Compensation)

VqLeads by 90° plus (Inductive Compensation)
Vq= Injected AC voltage
 The concept of series capacitive
compensation
• The basic idea of series capacitive compensation is to
decrease the overall effective series transmission
impedance from sending end to receiving end, i.e.
X in the
T h e e ffe ctive im p e d a n ce o f
tra n sm issio n lin e

K = T h e d e g re e o f th e tra n sm issio n lin e , ie

. .
K = X c/X 0 ≤k≤1
INTRODUCTION TO THE TMSLF2407 DSP
CONTROLLER
• The Texas Instruments TMS320LF2407 DSP Controller is a
programmable digital controller with a C2xx DSP central
processing unit (CPU) as the core processor .
• The LF2407 contains the DSP core processor and useful
peripherals integrated onto a single piece of silicon. The
LF2407 combines the powerful CPU with on-chip memory
and peripherals.
• The LF2407 DSP controller offers 40 million instructions per
second (MIPS) performance. This high processing speed of
the C2xx CPU allows users to compute parameters in real
time rather than look up approximations from tables stored
in memory.
•
• The “brain” of the LF2407 DSP is the C2xx core, the LF2407
contains several control-orientated peripherals onboard .
•
• The peripherals on the LF2407 make virtually any digital
control requirement possible.
•
• Their applications range from analog to digital conversion to
pulse width modulation (PWM) generation.
•
• Communication peripherals make possible the communication
with external peripherals, personal computers, or other DSP
processors.
 Brief listing of the different peripherals onboard the
TMS320LF2407 A

• Two Event Managers (A and B)

• General Purpose (GP) timers
• PWM generators for digital motor control
• Analog-to-digital converter
• Serial Peripheral Interface (SPI) – synchronous serial port
• Serial Communications Interface (SCI) – asynchrones serial
port
• General-Purpose bi-directional digital I/O (GPIO) pins
• Watchdog Timer (“time-out” DSP reset device for system
integrity)
Joint Test Action Group (JTAG) Port

• The JTAG port provides a standard method of interfacing a

personal computer with the DSP controller for emulation
and development.
• The XDS510PP or equivalent emulator pod provides the
connection between the JTAG module on the LF2407 and
the personal computer.
• The JTAG module allows the PC to take full control over the
DSP processor while Code Composer Studio TM is
running.

PC to DSP connection scheme

Memory
• There are three main blocks of memory which are present on
the LF2407 chip: B0, B1, and B2.
• Additionally, there are two different memory “spaces”
(program, data) in which blocks are used.
• The LF2407 has 544 16-bit words of on-chip DARAM that are
divided into three main memory blocks named B0, B1, and
B2.
• In addition to the DARAM, there are also 2000 16-bit words
of SARAM.
• The main difference between DARAM and SARAM is that
DARAM memory can be accessed twice per clock cycle
and SARAM can only be accessed once per cycle. Thus,
DARAM reads and writes twice as fast as SARAM.
Memory Allocation Spaces

• The LF2407 DSP Controller has three different allocations of

memory it can use.
1. Data memory space.

2. Program memory space.

3. I/O memory space.

 Data space is used for program calculations, look-up tables,

and any other memory used by an algorithm. Data memory
can be in the form of the on-chip random access memory
(RAM) or external RAM.

The Components of the C2xx DSP Core

• The DSP core (like all microprocessors) consists of several

subcomponents necessary to perform arithmetic operations
on 16-bit binary numbers.
• A 32-bit central arithmetic logic unit (CALU).
• A 32-bit accumulator (used frequently in programs).
• Input and output data-scaling shifters for the CALU.
• A (16-bit by 16-bit) multiplier.
• A product-scaling shifter.
• Eight auxiliary registers (AR0 – AR7) and an auxiliary register
arithmetic unit (ARAU).
Memory Addressing Modes

• There are three basic memory addressing modes used by the

C2xx instruction set. The three modes are:
• Immediate addressing mode (does not actually access
memory)
1. Short-immediate addressing. The instructions that use short-
immediate addressing have an 8-bit.
 LACL #44h
2. Long-immediate addressing. Instructions that use long-immediate
addressing have a 16-bit constant as an operand.
 LACC #4444h
•
• Direct addressing mode
• In direct addressing, data memory is first addressed in blocks of 128
words called data pages. The entire 64K of data memory consists
of 512 DPs labeled 0 through 511 .
• The DP of a particular memory address can be found easily by
dividing the address (in hexadecimal) by 80h.
• Indirect addressing mode
• Indirect addressing is a powerful way of addressing data
memory. When using indirect addressing you load the
memory space that you would like to access into one of the
auxiliary registers (ARx). The current auxiliary register acts
as a pointer that points to a specific memory address.
•
General Purpose (GP) Timers

• A General Purpose (GP) timer is simply a 16-bit counter,

which may be configured to count up, down, or
continuously up and down.
• There are two GP
• Timers in each EV: Timer1 and Timer2 for EVA and Timer3
and Timer4 for EVB.
• The GP Timers include: setting the sampling period for the
ADC by triggering the start of conversion; or providing the
switching period for the generation of a PWM signal.
Shows a block diagram of a GP Timer. There are two cases that
1. When “x” = 2, “y” = 1 and “n” = 2
2. When “x” = 4, “y” = 3 and “n” = 4

General purpose Configuration Diagram

 Each GP Timer consists of the following components

• One readable and writeable (RW) 16-bit up and up/down counter register
• TxCNT (x = 1, 2, 3, 4). This register holds the current count value and

increments or decrements depending on the direction of counting
• 16-bit timer compare register, TxCMPR (x = 1, 2, 3, 4)
• 16-bit timer period register, TxPR (x = 1, 2, 3, 4)
• 16-bit individual timer control register, TxCON (x = 1, 2, 3, 4)
• Programmable input clock divider (pre-scaler) applicable to both internal
• and external clock inputs
• One GP Timer compare output pin, TxCMP (x = 1, 2, 3, 4)
• Interrupt logic
PWM Technique
• GP Timer Period Registers (TxPR) – User Specified Value
Addresses 7403h (T1PR), 7407h (T2PR), 7503h (T3PR),
7507h (T4PR)
• The period register determines the rate at which the timer
resets itself or changes direction (the period of the timer).
• This register in combination with the input clock frequency
(and clock pre-scale factor) determines the frequency of a
PWM signal created by the compare output pin.
• The corresponding timer either resets to “0”, or starts counting
downward (depending on the operating mode) when a
match occurs between the period register and the timer
counter (TxCNT).
Hardware Pictures With DSP
 DSO Result Using With DSP

For single phase open loop control of Inverter and output wave form with Resistive load
Resistive Load = 50 ohm
Input DC Supply = 5 volts.
Output Voltage = 3.076 volts.
 SPWM Technique with Analog Circuit
based

e Control Circuit for open loop Single Phase Inverter with Sinusoidal PWM
Hardware Pictures With Analog Circuit
SPWM Signal
Output of the Inverter with Resistive Load


 THANK
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