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ET4254 RFIC Design, by L.C.N.

de Vreede, 2015

Power Amplifiers
Leo de Vreede

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Introduction

As final stage in the transmit chain the PA is typically the most power hungry component and the limiting function block for the
linearity performance.
Efficiency & Linearity are the design key parameters.

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Introduction (cont)
Base Stations

Handset

Standby-time
High linearity
Low DC power cons.

Conv. RF front-end
Expensive
Large form factor
Switch losses
Operation Costs
High Efficiency
Trends
High Linearity
Higher bandwidths & operational frequency
Higher peak-to-average ratios
Multi-band Multi-mode operation!!!

Talk Time
High Efficiency
High Linearity

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Outline
Introduction
Figures of Merit of PAs
Efficiency, and Power Added Efficiency (PAE)
Compression and Saturation power
AM/AM & AM/PM distortion
EVM and ACPR

Amplifier Classes
High Efficiency Amplifier Concepts
Conclusions
4

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Efficiency () &
Power Added Efficiency (PAE)

The efficiency of an power amplifier (PA) is an important design parameter,


it provides information on the talk time for a handset or operating cost of a
basestation amplifier.

Collector or Drain efficiency

P
RF output power (W)
out
consumed DC power (W) PDC

Power Added Efficiency

RF output power (W) - RFinput power (W) Pout Pin


1

consumed
DC
power
(W)
P
G
DC
p
into
The PAE is a more realistic measure of the amplifier since it also takes
account the that is delivered to the input of the amplifier

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Pout & Efficiency


Typical relation between output power
and efficiency for a linear amplifier (e.g.
class-B)
PA provides highest efficiency when
providing maximum output power
Note that a modern complex modulated
signal only occasionally reaches its peak
output power conditions
Average efficiency is therefore much
lower.
The basic amplifier classes only result in
different peak efficiencies & linearity
performance, they provide no solution for
the efficiency drop versus power back-off

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

PA Eff. & Complex Modulated Signals


OFDM constellation diagram

OFDM signal in time domain


Amplifier must be able to handle the peak powers of the broadcast signal.
Most of the time the amplifier will operate at lower output power levels yielding a significantly lower
efficiency than the peak efficiency.
Amplitude fluctuations in the broadcast signal require the PA to be linear (low AM-AM distortion)
Also the phase transfer of the amplifier should not change with the power level (low AM-PM distortion)

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

AM/AM & AM/PM distortion


Gain expansion

Gain compression

When reaching the compression point the gain and phase transfer of the PA will start to
fluctuate
This yields distortion of the to be broadcasted signal
8

Pre-match
fundamental

S21 [dB], S21 [deg]

AM/AM & AM/PM distortion, FETs


Square-Law Optimization LDMOS
PA
Before optimization
2

-10

-20
-30

-2

-40

IM3

-4

-50

-6

-60

-8

-70
-5

15

25

35

IM3 [dBc]

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

45

Pout [dBm]

Harmonic terminations
@ fIF and f2nd
LDMOS amplifier with trans-conductance
shaping using VG-offsets
Variations in S21 vs. power is equivalent
9 to:
AM-AM & AM-PM distortion

-10

-20

-30

-2

-40

20dB imp.

-50

-4

IM3

-60

-6

-70

-8
-5

15

25
Pout [dBm]

35

45

S21 [dB], S21 [deg]

After optimization

Active devices

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

AM-AM & AM-PM distortion

Effective fund. Ampl.


(reduced gain in when
in compression)

In this example, the signal clipping also changes the phase of the output signal
(phase change is measured
at the zero crossings)

10

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

EVM & ACPR

An error vector is a vector in the I-Q plane between the ideal


constellation point and the point received by the receiver.
EVM = average power of the error vector, normalized to signal power

11

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

EVM & ACPR

The error vector magnitude is equal to the ratio of the power of the
error vector to the root mean square (RMS) power of the reference. It
is defined in dB as:

or

where Perror is the RMS power of the error vector. For single carrier
modulations, Preference is, by convention, the power of the outermost
(highest power) point in the reference signal constellation. More
recently, for multi-carrier modulations, Preference is defined as the
reference constellation average power.
In the case of a set of values

the RMS value is given by:

12

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

EVM & ACPR


ACPR or ACLR
The adjacent channel power ratio, or adjacent channel leakage ratio
defines the ratio between the total power in the adjacent channel
(intermodulation signal) to the main channel's power (useful signal).

This is a very important parameter of


broadcasting PAs since its bounded
by strict regulations to avoid channel
to channel interference

13

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

The Amplifier Classes


Ideal Device operation
The Amplifier Classes
Current source operation active device
Class-A, AB, B, C & Class F

Switch mode operation active device


Class E
Class D

Wideband high efficiency operation


Inverse classes
14

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-A, AB, B & C operation


Current source like behavior of the active device
Ohmic loading conditions for the device at the Intrinsic reference
plane.
Reference plane output
Intrinsic device (L)

Reference plane
external circuit (Lext)

vin
gm.vin

Loading conditions at f , 2f ,
3f0,4f0 etc. determine the
waveform shape at the output

Output capacitance & bondwires

0
0 with output parasitics
Ideal current source like device

15

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-A, AB, B & C operation


When the input drive of the active
device (FET) for a part of the cycle is
below Vt the related Id of the FET
device goes to zero.
Consequently, the devices conducts
only a part of the sinusoidal angle. [1]
t = angular frequency
= conduction angle
Vg= gate voltage
Vt = threshold voltage of the FET
Vq= quiescent gate voltage
Iq = quiescent drain current
Imax = maximum drain current
Class

Gate bias point

A
AB
B
C

0.5
0-0.5
0
<0

Quiescent
current
0.5
0-0.5
0
0

Conduction angle
2pi
Pi-2pi
pi
0-pi

Table: Bias point and conduction


angle of different classes (the
signal voltage and current swing
are normalized to 1)
16

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-A, AB, B & C operation


Vsupply

Relation between output bias current and the bias input voltage for the various amplifier classes.
The lower the quiescent current (ICE,q) the higher the potential power added efficiency, but linearity
decreases.
Proper device optimization combined with harmonic termination might improve the linearity in classAB / class-B

17

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Chock
inductor
v (t ) L

Class-A, AB, B operation


For class-A, -AB,-C, the
voltage swing goes up
to twice the supply
voltage

Vdd normalized to 1

di (t )
dt

(Harmonic)
Matching
Network

ZL

In class A (harmonic
terminations are equal to Zfund)
In class-AB, B and C (harmonic
terminations are shorted)

Voltage swing can be


higher for other classes
using non-shorted
conditions for the
harmonics. E.g.:
class-E or class-J.
This yields higher
voltage stress for the
active device

18

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-A operation
Transistor is always on (conduction
angle = 2, transistor acts as a current
source all the time, yielding the
highest linearity of all classes.
Swing drain current for class-A
operation should be between zero and
Imax (Imax = saturation current
transistor). The voltage swing of the
drain should be between zero and the
device breakdown voltage.
Since there is always a combination of
voltage and current over the device, it
is consuming power all the time low
efficiency.

Drain voltage and Drain current in


class-A operation
19

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class A


using an ideal device
Class-A amplifier

In this example an ideal device is used for the active device.


The gm of this device = 10
The maximum input voltage of the device (Vmax = 1V) beyond this value the output current will saturate to 10A (IMax=10A)
In class A the quicent current is set to 0.5 x Imax = 5A
Since the device is biased at 10V at its output terminal, the amplitude of the aimed voltage swing is also 10V
Consequently, the optimum loading resistance for max power out is Ropt= 10V/5A=2ohm

VDC
I_Probe
IDCsource

HARMONIC BALANCE
HarmonicBalance
HB1
Freq[1]=1.0 GHz
Order[1]=9
SweepVar="Vin"
Start=0
Stop=1
Pt=

DC_Feed
DC_Feed1

vload
I_Probe
vdev
Idev

V_1Tone
SRC3
V=polar(Vin,0) V
Freq=1 GHz
V_DC
SRC4
Vdc=0.5 V

V_ DC
SRC2
Vdc=10.0 V

Var
Eqn

DC_Block
DC_Block2

I_Probe
iload

R
R1
R=2 Ohm

ideal_device
X1
gm=10
VAR
VAR1
Vin=1

20

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class A

Eqn PDC=real(VDC[0]*IDCsource.i[0])
Eqn Pout=0.5*real(vload[1]*conj(iload.i[1]))
Eqn eff =Pout/PDC

Here the device hits saturation

10.000

using an ideal device

50

8.333

DC power is const.

40

6.667

Pout
PDC

30
5.000

20
3.333
10

1.667

0.000

0
0

10

12

14

16

18

20

22

0.0

0.1

0.2

0.3

0.4

ts(vdev)

0.6

0.7

0.8

0.9

1.0

Vin

25

0.8

m1
Vin=0.500
eff =0.500

20
0.6

For practical devices one


should be aware of Vmin
(Vknee), Vmax, Imax and
Pdis max

m1

15

eff

ts(vdev), V

0.5

device overdriven
output volage and
current no longer
pure sinewaves

0.4

10
0.2

0.0
0.0

0.2

0.4

0.6

0.8

1.0

time, nsec

1.2

1.4

1.6

1.8

2.0

0.0

0.1

0.2

0.3

0.4

0.5

Vin

0.6

0.7

0.8

0.9

1.0

21

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-B Operation

The class B amplifier has half-sine


drain current waveform and the drain
voltage waveform is full-sine wave.
Compared to class A the overlap of
the drain current and voltage is less,
yielding lower DC dissipation and
therefore higher efficiency.

Linearity of class-B operation can be


with, pworse
id (t ).vds (t )
good but is in general
dis ( t ) than
that of class-A.
All higher harmonics are shorted!

Drain voltage and Drain


current of class-B operation
22

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class-B


using an ideal device
Class-B amplifier
In this example an ideal device is used for the active device.
The gm of this device = 10
The maximum input voltage of the device (Vmax = 1V) beyond this value the output current will saturate to 10A (IMax=10A)
In class B the quicent current is set to 0A
Since the device is biased at 10V at its output terminal, the amplitude of the aimed voltage swing is also 10V
In this situation the output power is set through the value of the load resistance for the fundamental, all higher harmonics are shorted.
The maximum output power is set by the maximum output current of this ideal device (10A), trying to get more output power will lower the efficiency.
The optimum resistance for maximum power out (limited by Imax) and efficiency = 2 ohm for the fundamental load

HARMONIC BALANCE
HarmonicBalance
HB1
Freq[1]=1.0 GHz
Order[1]=15
SweepVar="Vin"
Start=0
Stop=0.6
Pt=

V_1Tone
SRC3
V=polar(Vin,0) V
Freq=1 GHz
V_DC
SRC4
Vdc=0.0 V

Var
E qn

VDC
I_Probe
IDCsource

V_DC
SRC2
Vdc=10.0 V

DC_Feed
DC_Feed1

vload

ideal_device
X1
gm=10
VAR
VAR1
Vin=1

All higher harmonics at the


output are shorted!

vdevI_Probe
Idev

DC_Block
DC_Block2
Var
E qn

Var
E qn

VAR
VAR4
Vsup=10V
Imaxdev=10A

I_Probe
iload

VAR
VAR3
ffund=1.0GHz
Ropt=2*Vsup/Imaxdev
Xfund=0
Xsecond=0
zfund=Ropt+j*Xfund
zsecond=Xsecond*j
zthird=0

Z1P_Eqn
Z1P1
Z[1,1]=if (freq<=ffund) then zfund else if (freq<=2*ffund) then zsecond else zthird endif endif

23

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class-B


using an ideal device
14

25

12

0.6

ts(vdev), V

8
6
4

15

eff

ts(Idev.i), A

m1
Vin=0.500
eff=0.784

20

10

10

0.4

0.2
0

0
-2

-5

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0

0.0
0.2

0.4

0.6

time, nsec

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0

0.1

0.2

time, nsec

14

35

12

30

10

25

Pout
PDC

ts(Idev.i)

m1

0.8

20
15

DC

4
10

-2

0.4

0.5

Eqn P DC=real(VDC[0]*IDCsource.i[0])
Eqn P out=0.5*real(vload[1]*conj(iload.i[1]))

Eqn eff=P out/P DC

Pout increases
quadratic

0
-2

10

12

ts(vdev)

14

16

18

20

22

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Vin

The device gets overdriven at Vin is 0.6V

0.6

Vin

ies
r
va
r
e
w
po

0.3

24

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Calculation Spectral Components


Class-A, AB, B, C

The drain current for an amplifier with reduced conduction angle:


id ( ) (1)
Iq Ipk . cos , / 2 / 2
0, for / 2
and
/2
With: Id =
draincurrent,
Iq =

quiescent current,

Ipk =

amplitude of drain current,

Imax =

the peak value of drain current,

is the conduction angle.

Note that
and
Iq
cos( / 2)
Ipk
Substitution in (1) yields Iafter
some
pk
manipulation

I max Iq

Imax
i
d
(

cos(
/ 2)) the related DC current, as
Using a Fourier decomposition.(cos
we can
calculate
1 and
cos(harmonic
/ 2)
well the fundamental
current components
25

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Calculation Spectral Components,


Derivation id()
Derive the equation for id() in terms of the conduction angle and Imax:

id ( ) Iq Ipk . cos id ( ) Ipk . cos cos


2

Using also the fact that (eliminating Iq):


We can write that:

Yielding:

Using Iq=-Ipk.cos(/2)

I pk cos( / 2) I max I pk I q

I max
I pk
(1 cos( / 2))

I max

id ( )
. cos cos
(1 cos( / 2))
2
26

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Calculation Spectral Components


Class-A, AB, B, C
The DC component is

/2
I max
1
Idc
.
.(cos cos( / 2))d
2 / 2 1 cos( / 2)

Idc

I max 2.sin( / 2) .cos( / 2)

.
2
1 cos( / 2)

The magnitude of nth harmonic is:


/2
I max
1
In .
.(cos cos( / 2)).cos( n ) d
/ 2 1 cos( / 2)

So, the fund. of the drain current is (n=1)

I fund

I max sin

.
2 1 cos( / 2)

27

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Spectral Components
Class-A, AB, B, C

Depending on the
conduction angle the
amplitude of the DC,
fundamental and
harmonic components
of the drain / collector
current can be
influenced

28

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Efficiency Class-A,

From the spectral components we can calculate the efficiency


Consequently, for class-A (=2)

I DC

I max

Vmax
VDC
The DC dissipation power of class-A operation power amplitude:
2
The output power for class-A operation:

Pdc Vdc. Idc

I fund
Vfund

I max
2

Vmax
2

Vmax . I max
4

The maximum drain efficiency of class-A operation:

V .I
1
Pout V fund .I fund max max
2 drain efficiency 50%.
8
So, for class-A operation, the maximum

Pout 1
50%
Pdc 2

29

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-B Operation
Ic

Class-B
Load line
Foerier components current

Ic I max [1/ 1/ 2sin(t )

Vcc

2Vcc

an cos( nt )]

n 2,even

(1) n 1 1
with: an 1/
n2 1
Theoretical efficiency = /4
(ignoring knee voltage)

Shorting all Zn (n>1) all Vn = 0


pure sine wave for V

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Efficiency Class-B,
Consequently, for class-B(= )
(Using the eq. of page 27)

I DC

I max

VDC

V max
2

I max
2
V max

I fund
Vfund

The DC dissipation power of class-B operation power amplitude:


dc Vdc . Idc
The output power for class-BPoperation:

Vmax . I max
2

V .I
1
The maximum drain efficiency
Poutofclass-B
V operation:
.I
max max
2

fund

fund

So, for class-B operation, the maximum drain efficiency 78.5%.

Pout
78.5%
Pdc 4

31

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Efficiency Class-AB & Class-C


Class AB:
Class AB is a compromise between class A and
B. is between and 2. Typically, the larger
, the better the linearity, however the lower
the efficiency and vice versa. So, its theoretical
maximum drain efficiency is between 50% and
78.5%.
Class C:
In Class C operation is between 0 and .
Theoretically 100% drain efficiency can be
reached (=0). However, this also means that
there is no power deliver to the load. So, a
trade off between efficiency and output power
must be made.
Drain voltage and Drain current
32
of class-C operation [1]

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Linearity Class-AB & Class-B


Perfect class-B operation, yields no 3rd order
distortion (zero), in practice often class-AB is
preferred for manipulating the IM3 sweet spot
close to the 1dB compression point
Therefore also the choice of the Gate bias point /
quiescence current is used in this linearity
optimization
Shorted condition for harmonics and baseband
yields lower memory effects.
33

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Linearity Class-AB & Class-B


LDMOS behavior (1)

Taylor series description:


2
4
5
IDS (VGS ) g mv gs g m 2v gs
g m 3v g3s g m 4v gs
g m 5v gs
K g mnv gns

0,4

0,6

Class AB
(optimum)

0,4

This sets Iq

gm

0,3
0,2

IDS

0,2

0,1

gm3

-0,2

-0,1
3

VGS [V]

gm [A/V], gm3 [A/V3]

IDS [A]

0,8

v gs VS cos t
or
v gs VS (cos 1t cos 2t )
One or two tone excitation

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Linearity Class-AB & Class-B


LDMOS behavior (2)
Single-tone response

Two-tone response

at 2 GHz

at 2 GHz
IM3 [dBc]

Mag(S21) [dB]

100
14
:
60
12
:
40
10
mA-5
-10

AM-AM

Increasing IDQ

16

G
p

-10
-20

Increasing
IDQ

-30
-40
-50

IM
3

-60
0

10

15

20

3
5
g m 3VS2 g m 5VS4
4
8

Linear gain

IM 3

12
10
8
6
4

10 15 20 25 30 35 40

Pin-NWA [dBm]

AM-AM S21(VS ) g m

14

Gp [dB]

16

Po,IM 3
Po,FUND

Pout-avg [dBm]
3
25
g m 3VS3
g m 5VS5
4
8

9
25
g mVS g m 3VS3
g m 5VS5
4
4

Plotting the gain vs. input power gives info on the AM-AM and IM3 behavior

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-F

The major difference with class-B is the open conditions of the odd higher harmonics, this yields
squaring of the output voltage wave
This reduces the overlap between the voltage and current waveforms at the device output improved
eff.

36

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class-F


using an ideal device
In this design there are 7 harmonics controlled at the output of the device
Clas s -F amplifier
In this example an ideal devic e is us ed for the ac tive devic e.
The gm of this devic e = 10
The maximum input voltage of the devic e (Vmax = 1V) beyond this value the output c urrent will s aturate to 10A (IM ax=10A)
In c las s -F the quic ent c urrent is s et to 0A
In Clas s -F the even harmonic s are s horted the odd harmonic s are open
Sinc e the voltage waveform approximates a s quare wave maximum voltage at full power the fundamental amplitude will be
higher then the s upply voltage with a maximum of 4*Vs upply/pi=1.27*Vs upply
Var
Eqn

HARMONIC B ALANCE
VDC
Harmonic Balanc e

SRC3
V=polar(Vin,0) V
Freq=1 GHz
V_ DC
SRC4
Vdc =-0 V

Var
Eqn

Vs up=10V
Imaxdev=10A
Var
Eqn

Vdc =Vs up

L1
L =100.0 nH
R=

Start=0
Stop=1
Pt=

V_ 1Tone

V_ DC
SRC2

I_ Probe
IDCs ourc e
L

HB1
Freq[1]=1.0 GHz
Order[1]=7
SweepVar="Vin"

VAR
VAR4

vdev

ideal_ devic e
X1
gm=10

I_ Probe
Idev

z fund=RoptB*(1)
z 2=0
z 3=100
z 4=0
z 5=100
z 6=0
z 7=100

vload
DC_ Bloc k
DC_ Bloc k2

VAR
VAR4
ffund=1.0GHz
RoptB=2.0*Vs up/Imaxdev

I_ Probe
iload

Z1P_ Eqn

z 8=0

Z1P1
Z[1,1]=if (freq<=ffund) then z fund els e if (freq<=2*ffund) then z 2 els e if (freq<=3*ffund) then z 3 els e

VAR
VAR1
Vin=1

37

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation Class-F


using an ideal device
In this design there are 7 harmonics controlled at the output of the device
EqnPDC=real(VDC[0]*IDCsource.i[0])

Eqneff=Pout/PDC

EqnPout=0.5*real(vload[1]*conj(iload.i[1]))

Eqnzload=vload/iload.i

14

50

100

12

Drain current

6
4

80

real(zload)

mag(vdev[::,1])
Pout
PDC

ts(Idev.i), A

m3
Vin=0.710
mag(vdev[::,1])=12.321

40

10

30

20

m3

2
10

60

m2
nothing= <invalid>
real(zload)=<invalid>

40

zload

20

m2

-2

0
0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-20
0.0

0.1

0.2

0.3

0.4

time, nsec

0.5

0.6

0.7

0.8

0.9

1.0

25

freq, GHz

m1

1.0

14
12

20

0.8
10
0.6

10

eff

ts(Idev.i)

15

eff

ts(vdev), V

Vin

m1
Vin=0.630
eff=0.962

0.4
5

loadline

8
6
4
2

0.2

Drain Voltage

-5
0.0

0.2

0.4

0.6

0.8

1.0

time, nsec

1.2

1.4

1.6

0
0.0
1.8

2.0

-2
0.0

0.1

0.2

0.3

0.4

0.5

Vin

0.6

0.7

0.8

0.9

1.0

-2

10

12

ts(vdev)

14

16

18

20

22

38

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-F
More than 3 harmonics are difficult to control in practice,
three controlled harmonics yields 90% eff. as practical limit
The control of more harmonics tends to make the design
narrowband

Data from S.C. Cripps

39

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-E
The essence of class-E is a transistor in switch-mode driving a tuned LC tank circuit

o Switch-Mode operation: No simultaneous voltage and current appearing on the


device up to 100% efficiency
o Resonator at the load filters out the harmonic components
o Soft switching: No charge/discharge losses during switching
PRO Simple hardware implementation
CONT Higher voltage swing on active device
No modulation of Pout possible without additional measures
40

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-E

The first condition is needed to obtain the highest efficiency (ideal case, with ideal
components)
This second condition is mainly used to get sufficient boundary conditions to solve
the system of differential eq. (note that when this derivative is zero there is no current
41
flowing. There are some papers that claim that using this solution that it yields a
lower sensitivity of the circuit on component spread)

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation class-E


using an ideal device
Class-E amplifier
In this example an ideal device is used for the active device.
The gmof this device = 10
The maximuminput voltage of the device (Vmax= 1V) beyond this value the output current will saturate to 10A (IMax=10A)
In class E the quicent current is set to 0A
The voltage amplitude in class-E is significantlyhigher than the supplyvoltage e.g. up to 4 times
All harmonics are reactively(inductively) terminated

HARMONIC BALANCE

DC_Feed
DC_Feed1

HarmonicBalance
HB1
Freq[1]=1.0 GHz
Order[1]=32
SweepVar="Vin"
Start=0.2
Stop=0.3
Pt=

V_DC
SRC2
Vdc=10.0 V

vload
vin

V_DC
SRC4
Vdc=0.0 V

VDC
I_Probe
IDCsource

Vf_Pulse
SRC5
Vpeak=Vin V
Vdc=0 V
Freq=1 GHz
Width=0.5 nsec
Rise=0.01 nsec
Fall=0.01 nsec
Delay=0 nsec
Weight=no
Harmonics=16

ideal_device
X1
gm=10
Var
Eqn

VAR
VAR1
Vin=1

vdevI_Probe
Idev

L
C
L1
C2
C=3.2 pF {t} L=8.7 nH {t}
C
R=
C1
C=5.34 pF {t}

I_Probe
iload

Var
Eqn

R
R1
R=Ropt Ohm

VAR
VAR4
Vsup=10V
Imaxdev=10A

Var
Eqn

VAR
VAR3
ffund=1.0GHz
Ropt=4.95 {t}

42

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

ADS simulation class-E


using an ideal device
Eqn P DC=real(VDC[0]*IDCsource.i[0])

Eqn Zinternal=vdev/Idev.i

Eqn P out=0.5*real(vload[1]*conj(iload.i[1]))

Eqn RL=4.95
Eqn Gammainternal=(Zinternal-RL)/(Zinternal+RL)

Eqn eff=P out/P DC


60

350
300

48

m2
ts(vdev), V

200
150
100
50

4.8

36

3.6

24

2.4

12

1.2

secondharm
freq=2.000GHz
Gammainternal=1.006 / 30.621
Vin=0.300000
impedance =Z0 * (-0.046 +j3.652)

ts(Idev.i), A

ts(vin), mV

250

thridharmonic
freq=3.000GHz
Gammainternal=1.002 / 49.849
Vin=0.300000
impedance =Z0 * (-0.005 +j2.152)

6.0

m2
time=685.5psec
ts(vdev)=38.829
Vin=0.240000

thridharmonic

0
0

-50
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0
0.0

2.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

secondharm

2.0

time, nsec

time, nsec
4

14.9

14.8

14.7

1.0

Gammainternal

0.0

0.9
0.8

Pout
PDC

0.6
0.5

14.6

14.5

-1

14.4

0.4

eff

ts(Idev.i)

0.7

fund
fund
freq=0.0000Hz
Gammainternal=0.154 / 0.000
Vin=0.300000
impedance =Z0 * (1.365 +j0.000)

0.3
0.2
0.1

-5

10

15

20

ts(vdev)

25

30

35

40

0.0
0.20

0.22

0.24

0.26

0.28

0.30

freq (0.0000Hz to 32.00GHz)

Vin

43

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Implementation Example Class-E

60W wideband class-E amplifier


using bondwire based matching
networks
44

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Wideband PA operation
High efficiency operation requires well controlled
harmonics vs. frequency
This proves to be difficult over a large bandwidth,
e.g. class-B with transmission line stubs to
implement the 2nd harmonic short circuit
conditions
However there seems to be also a continuous
solution for high efficiency (78.5%) operation
using the fundamental and second harmonic
termination only
45

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Class-J

Uses reactive loading for fundamental and second


harmonic, namely:
Z Fund _ J RFund _ B (1 j ) ,
with

Z Sec _ J mj

3
RFund _ B
8

RFund _ B 2VDD I peak

All higher harmonics are shorted


Higher voltage swing
2 2 Vds on the active device
Exactly the same efficiency as class-B
There proofs to be a continuum of high efficiency
operation from class-J through class-B to class-J*

46

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Wideband Matching for 78.5% Efficiency


(Solution I)

class-J

class-J*

Class B

class-B

Class B
class-J*

47

class-J

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Wideband Matching for 78.5% Efficiency


(Solution II, more practical)

48

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Voltage Waveforms Class-B, Class-J & Class-J*

There are several solutions between Class-B and Class-J that


all yield a class-B like efficiency (78.5%)
class-J*

class-J
3.0

b=-1 Class-J
b=-0.75
b=-0.5
b=-0.25
b= 0 Class-B
b=0.25
b=0.5
b=0.75
b= 1 Class-J

Voltage (V)

2.5

2.0

1.5

1.0

0.5

0.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

class-B

49

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

The Inverse Classes


Voltage and current wave forms
V
are interchanged

out

Iout

E.g. inverse class-B


Pure sinusoidal current
& rectified sin wave as voltage
wave.
Class-B operation
This inverse mode can be
Iout
achieved by using open harmonic Vout
loads in stead of shorted
harmonics.
Comparable conditions can be
found for inverse class-F etc.
Inv class-B operation

50

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

High Efficiency PA concepts


High Efficiency Principles
Load modulation concepts
Doherty
Outphasing
Dynamic load line
Supply voltage modulation concepts
Envelope Tracking (KANN)
Envelope Elimination and Restoration
Other techniques
51

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

High Efficiency Principles


Remember for
class-B

In power back-off a
conventional PA drops in
efficiency since for the given
output power level the output
voltage swing with respect to
the supply voltage is
reduced.
High efficiency amplifier
concepts maximize their
voltage swing with respect to
the supply voltage in power
back-off by dynamically
changing their load line or
their supply voltage.

Vout 2
Pout
2.R fund
Pdc Vdc. Idc ( Pout )

Vmax . I DC ( Pout )
2

Class-B
Load line modulation
different currents
still result in the
maximum voltage
swing
Supply voltage
modulation ensures that
the output stage is
always at its maximum
voltage swing

52

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Doherty PA operation principles


Invented in 1936 by W.H.Doherty;
Dynamic loading main PA yields two efficiency peaks vs. power back-off.
First 50kW DPA implemented in radio broadcast transmitter in 1938 based on vacuum
tubes; At 6-dB back off, the efficiency improved from 33% to 60%

Peaking amplifier activated

Always on (class-B)

main

W.H.Doherty, Proc. IRE, vol.24, no.9,


pp. 1163-1182, Nov.1936
53

Perfectly inphase
This peaking amplifier is only active
for the higher output power levels
(class-C)

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

DPA operation principles


Z1 decreases to Z0

Main PA
Maximum voltage
swing is maintained

Eq. valid for Symmetric


Doherty Only!!!
The impedance of the main PA is modulated by the current ratio I2/I1
When I2 =0 the RL is high and main PA reaches voltage saturation
quickly.
After reaching this point I2>0 and the effective loading of the main PA
reduces
Note that the constrains are given for symmetric DPA only, for
asymmetric DPAs I2 can be larger than I1

4
54

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

m a g (V in _ _ p e a k[::,1 ])
m a g (V in _ _ m a in [::,1 ])

DPA operation principles


Voltage sat. main PA
@ Pback-off

1.0

Imain

0.8

Currents generated by Main and Peak


device vs. normalized input
voltage,indicates at which back-off
condition the Main device turns on.

0.6

Ipeak

0.4

0.5

0.2

0.0
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Note that: I main @ back . I main @ max

m a g (V p e a k [::,1 ])
m a g (V m a in [::,1 ])

Vin

0.5

10

Vmain

Vpeak

Voltages at current generators

0
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Vin

m a g (Z p e a k )
m a g ( Z m a in )

10

Zpeak

Zmain

Resulting impedances

0
0.0

55

0.1

0.2

0.3

0.4

0.5

Vin

0.6

0.7

0.8

0.9

1.0

Maximum output level

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

0.5

DPA operation principles


Efficiency Vs. Output Power

0.8

Efficiency

0.6

Main

DPA

0.4

Peak

Voltage sat.
main PA

0.2
0.0
-20

Resulting efficiency of a symmetric Doherty


Amplifier ( = 0.5)

-15

-10

-5

Normalized Output Power


Efficiency Vs. Output Power
0.8

Efficiency

0.6

Comparison efficiency of a symmetric


Doherty Amplifier ( = 0.5)
with the efficiency as provided by a single
line-up class-B amplifier

DPA
0.4

Class-B

0.2

(added for comparison)


0.0
-20

-15

-10

-5

Normalized Output Power

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

DPA Design Procedure


Given:
Supply voltage main and peaking device (Vsup)
Class-B device operation
Maximum output power (Pmax)
Power back-off ratio high efficiency point (Pratio)
Step 1: Calculate power at high efficiency power back-off point, at this point the
Peak device is still switched off, so:

Pout @ back Pmain @ back

Pmax
10 Ratio _ in _ dB /10

Note that Imain increases linearly with the normalized input, while the related
output power increases quadratic, so the factor can be calculated as,

Pmain _ back Pmax


Consequently Imain@max can be derived from the power in back-off, using:

Pmain @ back 0.5( . I main @ max .Vsup )

57

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

DPA Design Procedure


Step 2: Calculate Ipeak_max

Pmain @ max

I main _ max .Vsup


2

Ppeak @ max Pmax Pmain _ max


Yielding:

I peak @ max

2 Ppeak @ max
Vsup

With Imain_max and Ipeak_max known, we can solve for the other unknown circuit
Conditions, namely; Ro and RL

58

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

DPA Design Procedure


Step 3: Calculate Ro and RL
Consider load conditions Main PA
at Pback and Pmax

Z main @ back
Ro 2
Z1
Z1 '

Vsup 2
2 Pmain @ back
with:

Z main @ max

RL
Main PA
Vsup 2
2 Pmain @ max

I2
Z1 ' (1 ) RL
I1 '

Considering the above in power back-off (I2=0) and at Pmax (I2=Ipeak_max)


and using the fact that at Pmax the voltage swing is equal to Vsup for both
the main and peaking device one can solve for Ro and RL

59

ET4254 RFIC Design, by L.C.N. de Vreede, 2015


Advanced implementations

12dB back-off

Two-way & Three way Doherty


In the mixed signal
approach each input is
driven individually by
using coherent RF input
signals.

Two-way DPA

This eases achieving the


desired current profile
versus power for each
stage.
No manipulation of the
bias points of the active
devices is now required
for Doherty operation.
The bias points are now
optimized for efficiency
only!
August 10, 2016

Three-way DPA

Eff. versus normalized input voltage


60
drive of an ideal class-B operated
twoway and three-way Doherty PA, which
are both optimized for max. efficiency
at 12dB Power back-off

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Three-Way Doherty,
Mixed signal testing

August 10, 2016

61

Hardware mixed-signal test setup

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Three-Way, GaN Doherty,


Measured Results
M. Pelk & E. Neo,
IEEE trans. on MTT, July
2008

August 10, 2016

62

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Outphasing Amplifier


Basic concept

Input AM signal is converted into


Two Anti-phase PM Signals

Present constant envelop signals to the


PA devices.

Ideally AM-AM and AM-PM distortion of


the PA devices should not affect the
linearity of the output.

Output can be linear irrespective of the


linearity of PA devices (LINC)

PA devices can be operated at saturation


yielding improved efficiency.
Linearity considerations assume the
use of isolating power combiner
yielding a poor system efficiency!!!

Can be class-E

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Outphasing Amplifier


Input signal with
varying envelope

S1 t

Sin t V t .cos[c t (t )]

Sin t

Vmax cos t cosct t

Vmax
cosct t t
2
Signals with a
constant envelope

G
Signal
Component
Separator

Non-Linear
RF PAs

S out t

GVmax cos t cos c t t


Amplified replica of
input signal with
varying envelope

V t

Vmax

t cos 1

S2 t

Vmax
cosct t t
2
S t
1

t
t

Sin t

t
S t
2

Remember:

cos( x) cos( y )

cos( x y ) cos( x y )
2

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Chireix Amplifier

Using a non-isolating power combiner


yields improved efficiency in power backoff, due to the complex load modulation
of the active devices in the PA output
stage

Voltage source like behavior of


PA devices is assumed.

The varying complex load can be made


real at a particular outphasing angle
resulting in efficiency peaking.

Overall:

Average Efficiency is higher. When


suseptance compensation is applied

Linearity is compromised due to nonzero interaction of PA devices.

2sin 2 ( )
sin(2 )
Y1
j
RL
RL
2sin 2 ( )
sin(2 )
Y2
j
RL
RL

For this topology the highest power is delivered


when branch signals are in opposite phase

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Chireix Amplifier


Y1

Y1

loading and efficiency without load compensation:

Y1,2

Y2

2cos 2
sin 2
Z 02

mj
with RL
RL
RL
RL

h = hB cos(Y) = hB cos f

Y2

loading and efficiency with load compensation:

Practical Chireixs amplifier topology


with transmissionline based power
combiner. The susceptances Cc, Lc
compensate the complex loading of
the PA stages at the specified
compensation angle

2cos 2
sin 2 sin 2c
Z 02

Y1,2
mj
with RL
RL
RL
RL
where c is the compensation angle
h= hB cos(Y ) = hB

For this topology the highest power is


delivered when branch signals are in phase

2cos 2 f
2

( 2cos2 ff) +( sin 2 - sin 2f c )

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Chireix Amplifier: No compensation


Loading of PA stages
2cos 2
sin 2
Y1,2 ( ) G ( ) mjB( )
mj
RL
RL
2
Z
with RL 0
RL

Efficiency of PA stages (no comp.)


h = h cos(Y) = h

Highest
output
power

Highest
output
power

G
2

G +B

= h cos f

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Chireix Amplifier with Comp.


Loading of PA stages
2 cos2
sin 2 sin 2c
G '( ) jB '( )
Y1,2
mj
RL
RL

Efficiency of PA stages
(with compensation)
h= h cos(Y ) = h
=h

G'
2

( G ') +( B ')

2 cos 2 f
2

( 2 cos2 ff) +( sin 2 - sin 2f c )

In the case of c =20

In the case of c =20

Highest
output
power

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Principle, Chireix Amplifier with Comp.


The output powers are independent of the compensation
2
2
2cos
f
Z
Pout = Vdc 2
where RL= 0
RL
RL

Large outphasing angles are


needed for a reasonable
output power control range

Load modulation

Output power vs. outphasing angle


Since for small output powers, two large vectors need to be subtracted, this concept is quite
sensitive for imperfections (inaccuracies) in the branch amplifier paths. Also the efficiency tends
to drop at large out-phasing angles due to the complex loading conditions, therefore restricting
the outphasing angle and using a combination of outphasing and input power modulation can
yield higher performance and less sensitivity of the final implementation (mixed-mode operation)

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Practical Implementations,
90 Watts GaN Amplifier

J. Qureshi, MTT-T 2009

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Practical Implementations,
90 Watts GaN Amplifier

Test setup

J. Qureshi, MTT-T 2009

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Practical Implementations,
90 Watts GaN Amplifier

Measured Efficiency & PAE

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Envelope Elimination and


Restoration (EER)

In this (Kahn) concept the PA is typically a saturated switch mode PA, the output power
modulation comes in through the DC supply.
Very high efficiency has been reported for this approach.
Large RF bandwidth
Video bandwidth of the DC-DC converter limits average efficiency for truly wideband signals.
73

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Envelop Tracking Amplifier

In EER concept all the amplitude information is handled through the


DC modulator, this makes the system difficult to implement
A simpler approach is the Envelop Tracking concept where the
amplitude information is still handled by the PA itself. The efficiency
improvement is achieved by the DC modulator that somewhat
tracks the slow envelope variations, keeping the PA stage close to
(but not in) voltage saturation

74

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Conclusion 1)
In 2009 Wireless networks alone are responsible for
0.5% of the worldwide C02 emission and their
contributions are expected to grow, if no appropriate
actions are taken

PAs dominate the power consumption of basestations!

75

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Conclusion 2)

Many PA classes and high efficiency concepts have been introduced

At this moment there is no clear winner in terms of operating class or


high efficiency concept, since there are many trade-offs in terms of:
Efficiency
bandwidth,
voltage stress active device,
linearity,
memory effects,
system complexity,
form factor,
and costs!

So there is still something to do for you..!


76

ET4254 RFIC Design, by L.C.N. de Vreede, 2015

Conclusion 3)

During the lectures you have been confronted with some basic as
well more advanced techniques, in order to shape you as a good
microwave engineer / scientist

For this purpose we have tried to give you a selection of the most
relevant information, homework problems and principle
understanding of the phenomena in microwave / RF circuits.

Please provide your feedback on the course to us, positive or


negativeas a whole or on specific parts

Success with your final homework problem and the exam.

Leo & Marco + PhD. students ELCA.


77