Leakage Current
Sept. 18, 2006
Power Challenge
Active power density increasing with
Problem Statement
Power Analysis on CMOS Inverter
char g e
Input
Input
Input
Cload
dis char g e
Problem Statement
Dynamic Power
Pswitching Cswitching VDD 2 f
in
(VDD 2Vth ) 3 f
12 VDD
gain _ factor: n p ,
Threshold _ Voltage: Vthn Vthp Vth
Problem Statement
Domination of Leakage Current
Feature
FeatureSize
Size
>>0.25um
0.25um
0.18/0.13/0.09um
0.18/0.13/0.09um
Performance(AP)
Performance(AP)
<<200MHz
200MHz
300/400/533MHz,
300/400/533MHz,1GHz
1GHz
Core
CoreVoltage
Voltage
5.0/3.3/2.5V
5.0/3.3/2.5V
1.8/1.2/1.0V
1.8/1.2/1.0V
VVTH(Threshold)
TH(Threshold)
>>+/+/-0.6V
0.6V
+/+/-0.5,
0.5,0.4,
0.4,0.3V
0.3V
TR
TRLeakage
Leakage
Negligible
Negligible
Exponential
Exponentialgrowing(SD/Gate)
growing(SD/Gate)
Stand-by
Stand-byMode
Mode
PLL-off(Clock-off)
PLL-off(Clock-off)
V/MTMOS,
V/MTMOS,High
HighVVTHTH/High
/HighVDD
VDD
Low
LowPower
Power
Focus
Focuson
onOperating
OperatingPower
Power
Focus
Focuson
onOperating/Stand-by
Operating/Stand-by
Turn of
Turn on
Sub-threshold Leakage
Source to drain tunneling
Vg=0V
Vd=Vdd
Vg=Vdd
Vd=0V
Gate oxide
tunneling
10
10
-1
10
Drain leakage
-2
10
-3
10
Gate leakage
-4
10
Cox
-5
10
-6
10
20
25
k0 A
Tphysical
30
Tox (A)
35
40
P VDD2
Low
Low VDD
VDD
I ds (VDD - Vth)1~2
Low Speed
Speed Up
Low
Low VVthth
High Leakage
Leakage
Suppression
I ds (VDD - Vth)1~2
VTH control
Dynamic power[W]
VDD control
High speed
10
MTCMOS
High speed
VDD: 1.5V
VDD control
1
VDD: 1.0V
Low speed
VTH control
Low speed
VTH: 0.5V
100n
1p
10p
VTH: 0.25V
100p
1n
10n
Leakage power[W]
100n
Variable-Threshold
Variable-ThresholdCMOS
CMOS
SchematicDiagram
Diagram principle
principle Merit
Merit Demerit
Demerit
Schematic
VDD
VDD
Low-Vth
Sleep
Hi-Vth
N-well
Low Vt
GND
P-well
Vpb = VDD
or V+
Vt
Control
circuit
Vnb = 0 or V-
GND
On-off
On-offcontrol
controlofofinternal
internal
VDD
or
VSS
VDD or VSS
Special
SpecialF/Fs,
F/Fs,Two
TwoVths
Vths
Threshold
Thresholdcontrol
controlwith
withbulk-bias
bulk-bias
Triple
well
is
desirable
Triple well is desirable
Low
Lowleakage
leakageininstand-by
stand-bymode.
mode.
Conventional
design
Env.
Conventional design Env.
Low
Lowleakage
leakageininstand-by
stand-bymode.
mode.
Conventional
design
Env.
Conventional design Env.
Large
Largeserial
serialMOSFET
MOSFET
ground
groundbounce
bouncenoise
noise
Ultra-low
voltage
region?(1V)
Ultra-low voltage region?(1V)
Scalability?
Scalability?(junction
(junctionleakage)
leakage)
TR
reliability
under
0.1m
TR reliability under 0.1m
Gate
Gateleakage
leakagecurrent
current
Vdd
Vdd
Normal or Low VTH MOSFET
Virtual Ground
Vss
0
Vss
High VTH switch
With High VTH switch, much lower leakage current flows between Vdd and Vss
High VTH MOSFET should have much lower ( >10X) leakage current compared to normal V TH
MOSFET
Current
Logic
Component Cutoff-Switch
(High Vth)
(Low Vth)
Operating
Mode Active
Sleep
Control
(SC)
VDD
Sleep
Low Vth
MOS
Active
SC
Time
VGND
VSS
High Vth
MOS
CCS Sizing
The effect of CCS (current-controlled switch) size
As the size decreases, logic performance also decreases.
As the size increases, leakage current and chip area also
increase.
Proper sizing is very important.
CCS size should be decided within 2% performance degradation.
VDD
Low Vt
Switch
Control
High Vt
GND
Vop = VDD - V
V must be sized
Leakage Current :
Limiting Factor in VDSM
Technology
C.M.Kyung
ITRS roadmap
Scaling down allows the same performance with reduced
voltage, leading to low power.
From 0.18 micron down, building a transistor with a good
active current(Ion) and a low leakage current (Ioff) is
difficult.
high-speed TRs ; low channel doping
low-leakage TRs ; high channel doping
PD(Partially Depleted)
Floating body effect increases speed
Low threshold in dynamic mode
or FD(Fully Depl)
Ideal subthresold swing of 60 mV/decade
Other tricks
Subthreshold current
Gate-induced drain leakage (GIDL)
Thermal emission
Trap-assisted tunneling
BTBT
Bulk punch-through
Fig 3.12
gate oxide ;
Using high K
Increases short-channel effects due to thicker gate
dielectric (This sets an upper limit on K, lower limit
coming from I tunnel)
Mobility degradation due to poor interface quality