The Five Classic

Components of a Computer
The Basic Computer Organization
 The Five Major Components:
1. Processor (Central Processing Unit CPU)
2. Memory
3. System Bus
4. Input Devices I/O Bus Memory Bus
5. Output Devices Processor

I/O Devices Memory

 Processor (CPU: Central Processing Unit)

 It is the brain of the computer
 It does all the computations
The Basic Computer Organization
 Memory:
 It is used to store the programs and data,
 It is an array of randomly accessible location,
 Each location is identified by a unique address

 I/O Devices:
 The processor communicates with the outside
world through the I/O devices (e.g. printer,
monitor, disk drive, sensors, etc.)
The Basic Computer Organization
 A Computer with a Direct Memory Access (DMA)
Controller:
I/O Bus Memory Bus
Processor

I/O Devices Memory

DMA

 The DMA Controller:

 Allows the transfer of data between the memory and I/O
devices without processor intervention,
 The processor can do some other useful CPU operations
The System Bus: Memory Bus
 The processor Address
communicates with the Processor Data
memory through the
Control
memory bus

 A memory bus consists of the following: Memory

 Address bus (Unidirectional)

 Data bus
 Control bus
The System Bus: Memory Bus
 The Data Bus (Bidirectional):
 This bus is used to transfer data between the
processor and memory,
 During a Write operation, the processor sends
data to the memory,
 During a Read operation, the memory sends
data to the processor,
 The Data Bus Size:
 Normally a data bus is: 8, 16 or 32 bits wide
depending on the processor
The System Bus: Memory Bus
 The Control Bus:
 The Control Bus is used to carry all the Control Signals
between a processor and its memory,
 Most of the individual signals are unidirectional:

Some are outputs from the processor,



 Others are inputs to the processor

 Typical Control Signals:

 Read/Write ( R / W )
 Address Strobe ( AS )
 Data Strobe ( DS )
 Data Transfer Acknowledge ( DTACK )
The Write Operation Control Signals
R/W = 0 → Write Operation

AS = 0 → Address Lines are Valid

Processor
DS = 0 → Activate Data Transfer

DTACK = 0 → Complete

 The Write Operation Steps: Memory

 The processor sends address through the address Bus
 The processor activates AS signal
 The processor sends low signal through R/W line
 The processor sends data through the Data Bus
 The processor activates DS signal
 The memory activates DTACK informing that data transfer is complete
The Read Operation Control Signals

R/W = 1 → Read Operation

AS = 0 → Address Lines are Valid

Processor
DS = 0 → Activate Data Transfer

DTACK = 0 → Complete

 The Read Operation Steps:

 The processor sends address through the address Bus
 The processor activates AS signal Memory
 The processor sends high signal through R/W line
 The processor activates DS signal
 The memory sends data through the Data Bus
 The memory activates DTACK informing that data transfer is complete
The System Bus: I/O Bus
 The processor communicates with I/O
devices through the I/O Bus
 Like the Memory Bus, the I/O Bus also
consists of Address Bus, Data Bus and
Control Bus,
 The Motorola’s processors share the same set
of Address Bus, Data Bus and Control Bus for
Memory and I/O Bus,
 The Intel’s processors share the same set of
Address Bus and Data Bus, but use different
Control Signals for Memory and I/O Bus
Memory Organization
AS Select Signal
0
Location 0
1 Location 1
n-bit m-bit
Address Bus Data Bus
Decoder

Location 2n-1
R/W
 The number of address lines = n
 # of addressable locations = 2n
 Word length = m bits
 # of lines in the data bus = m
Memory Types
 Read / Write Memory (known as RAM):
 Read and write operations are allowed,
 Volatile memory:
 The contents disappear when power is removed
 Read Only Memory (ROM):
 Contents can be read at any time but write
operation is allowed only once (by the
manufacture)
 Non –Volatile memory
 The contents are preserved even with power off
Memory Types
 Programmable Read Only Memory (PROM):
 Contents can be read at any time but write
operation is allowed only once (by the user),
 Non –Volatile memory
 Erasable Programmable Read Only Memory
(EPROM):
 Similar to PROM but it can be erased and
reprogrammed as many times as necessary,
 Information is erased by Ultra Violet light (slow),
 Non –Volatile memory
Memory Types
 Electrically Erasable Programmable Read
Only Memory (EEPROM):
 Similar to EPROM except that it can be erased
by electrical signals (faster)

 All the memory types described so far are

Random Access Memory (RAM), However,
the word RAM most commonly refers to
Read/Write memory only
The Processor
 Typically, the processor consists of:
 Arithmetic & Logic Unit (ALU),
 Registers
 Status Register (SR),
 Effective Address Register (EAR),
 Stack Pointer (SP),
 Instruction Register (IR),
 …….
 Control Unit (CU)
The Arithmetic and Logic Unit (ALU)
 Is responsible for all Arithmetic and Logic operations,
Input Input
Operand (1) Operand (2)

Select
Flags ALU Operation
Control Lines
 Function Select Lines:
 Select one of the functions that the ALU can perform

 Flags:
 The flag bit consist of Carry, Sign, overflow, etc…

 Size of an ALU:
 Indicates the size of an operation it can perform,

 For example, an 8-bit ALU can perform 8-bit arithmetic

and logic operations

The CPU Registers
 Status Register (SR):
 The flag bits of an ALU are stored in this register which
in turn can be accessed by the programmers,
 Program Counter (PC):
 It is a register that contains the address of the next
instruction to be executed by the CPU,
 Its contents can be changed by the programmers only
by the use of branch instructions,
 The processor sends the content of its PC to the
address bus when an instruction is to be fetched from
memory (indirectly through the EAR)
 The CPU Registers
 Effective Address Register (EAR):
 It is used internally by the processor to hold the address of a
memory location before the location is accessed for data transfer
operation,
 During data transfer operation the address bus is loaded from
this register
 Stack Pointer (SP):
 It is a register whose contents points to the top of the stack
 The stack is implemented in memory and used to save:
 The return address before jumping to a new subroutine,
 The CPU registers before the execution of a subroutine, and
 Intermediate results when evaluating expressions
The CPU Registers
 Instruction Register (IR):
 The instruction to be executed is loaded in this
register,
 The Control Unit will repeatedly decode the
contents of this register to decide on the
actions for the current instruction
The Control Unit
 This unit generates the internal control signals that
 cause registers to
 load data,

 increment or clear their contents,

 output their contents,

 cause the ALU to perform the correct function,

 The control unit

 receives the instruction code from the IR,
 receives the values of some flags from the SR,
 generates the signal of the system’s control bus
accordingly
The I/O Devices
 Wide variety of peripherals
 Delivering different amounts of data,
 At different speeds, and
 In different formats

 All slower than CPU and Memory,

 Thus, need I/O modules that are:
 Interface to CPU and Memory,
 Interface to one or more peripherals,
The I/O Devices
The External Devices (Peripherals)
 Human readable
 Screen, printer, keyboard, etc.
 Machine readable
 Monitoring and control

 Communication
 Modem, and
 Network Interface Card (NIC)
The External Devices (Peripherals)
Typical I/O Data Rates
I/O Steps
 Steps for Input Operation:
 CPU checks I/O module device status
 I/O module returns status
 If ready, CPU requests data transfer
 I/O module gets data from device
 I/O module transfers data to CPU