Cody Jackson*
Dr. Ashok Saxena** (advisor), Rahul Rajgarhia** (graduate student)
*Arkansas Tech University, **University of Arkansas, Fayetteville
Mechanical Engineering REU project presentation, July 23 2007
Outline
Background and Problem Statement
Proposed Solution
Experimental Procedure
Research Results
Discussion
Conclusions
Interconnects in Flip-Chip
Chip-to-package
interconnect
height
Silicon
Under fill
Substrate
pitch
Current Technology
2.
3.
4.
Reduced cost
Source: A. O. Aggarwal, P. Markondeya Raj, R. J. Pratap, A. Saxena, and R. R. Tummala, "Design and fabrication of high
aspect ratio fine pitch interconnects for wafer level packaging," 2002 IEEE Conference at Singapore, pp. 229-34 (2003)
Proposed solution
Higher mechanical strength than lead free solder and high cycle fatigue
resistance.
400
Stress (MPa)
Stress (MPa)
500
nanocrystalline copper
300
microcrystalline copper
200
100
0
0
0.005
0.01
0.015
Nanocrystalline Cu
Ultrafine grained Cu
Ultrafine grained Cu
Coarse grained Cu
0.02
Strain (mm/mm)
Tensile test
Nf (cycles to failure)
Source: S. Bansal, "Characterization of Nanostructured Metals and Metal Nanowires for Chip-To-Package Interconnections,"
in Materials Science and Engineering. Ph.D. dissertation, Atlanta: Georgia Institute of Technology, (2006).
Zama, S., D. F. Baldwin, et al. "Flip chip interconnect systems using copper wire stud bump and lead free solder." Electronics
Packaging Manufacturing, IEEE Transactions on 24(4): 261-268 (2001).
The Problem
Research
Nanocrystalline Cu was
produced using Equal Channel
Extrusion Process
Test specimen
1.2
5W
Research cont.
Load, kN
Resolution = 0.001mm
Range = + 2 mm
Time, ms
Research cont.
da dN vs K plot is known as
Paris Law.
When plotted on a log scale, there
is a linear segment known as the
Paris regime which allows the stress
intensity factor (K) to be related to
the sub-critical crack growth
independent of the specimen
geometry.
Using this plot, you can estimate
the life remaining in components due
to fatigue cracking.
Source: http://www.kuleuven.be/bwk/materials/Teaching/master/wg12/l1300.htm
Research cont.
K K o exp( .a )
K = Kmax Kmin (applied stress intensity parameter)
Ko= intial K (constant for a test)
a = ao a (crack increment)
= -0.08 mm-1 (normalized K gradient)
Data Analysis
da
dN
Results
Results
Comparison
Conclusion
Due to increased demand for smaller, more portable electronic devices, current
interconnect technology is not sufficient.
For example, a laptop may be turned on/off twice a day, five days a week, for five
years. This is a total of ~2600 cycles, on interconnects 25 x 10-3 mm. This gives
an approximate da/dN value of 9.6 x 10-6mm. Manufacturers can take estimates
similar to this and compare to current interconnect sizes to determine the
estimated life of certain components in their products.
Acknowledgments
Jeff Evans
Jeff Knox
Dr. Zou
Henry Wang